sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<whitequark> btw, when the board is not responding, it is not completely powe roff
<whitequark> the LCD is still on and displays one row of blocks
<whitequark> some LEDs are on too, but the fan is not spinning
<whitequark> it seems that the connector doesn't just disconnect everything but rather undervolts the board
<sb0> yes, you can also hear the fan speed change when you touch the connector
<sb0> and still in the department of crappy components, the power switch is shorted on
<sb0> and I've seen both those problems on other boards.
<sb0> I wonder if we should bother replacing that power connector (requires ordering the correct one, and then unsolder the broken one which uses large, plated-through holes that can be a pain)
<sb0> or just cut the power cord and solder it on the PCB
<sb0> well I guess the broken one shouldn't be too painful to unsolder: we can cut it and then pull the pins one by pne
<sb0> I'm not sure if the connector on the power supply or on the board is faulty though
<sb0> wtf, it's a molex part? I didn't know they made broken crap like that
<whitequark> sb0: I can desolder that connector very easily using that SMD rework low melting temp solder
<whitequark> I forgot how it's called for a moment
<whitequark> that's the same way I reworked my laptop's connector without hot air and its risks
<sb0> ok. but maybe it's the cable side anyway.
<whitequark> I do think it's the cable side.
<whitequark> there is basically nothing to break board side.
<sb0> whitequark, there should be a kc705 box behind the fridge
<sb0> with an adapter to put the kc705 in a PC (a silly thing to do, as this crap will fry your motherboard)
<sb0> you can take it apart and solder it to the power supply
<whitequark> ok, I will do that once I'm in the lab
<sb0> that other connector might be broken as well though
<sb0> our kc705 isn't the only one I've seen with power problems ...
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<sb0> ysionneau, why do you call flush() after opening the serial port?
<sb0> the pyserial doc says: "wait until all data is written". there was nothing written.
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<sb0> ysionneau, and why did you define _Tcube.send(), and sometimes use it, and sometimes do Message(...).send(self.port)?
<sb0> it's not even symmetric, i.e. there is no self.recv function ...
<sb0> this code is very sloppy
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<whitequark> sb0: the connector seems alright
<whitequark> the fan doesn't change speed when I touch it
<sb0> ysionneau, status_report_counter is only used in the subclass Tdc, therefore it should be initialized there, not in the parent class ...
<sb0> were you too lazy to overload __init__ or what
<sb0> ysionneau, why is there a move_stop function, when every other function is supposed to wait for completion?
<sb0> ditto is_moving
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<FabM> Hi, I've got a problem with quartus synthesis and Interface() object parameters
<FabM> If I declare an Int parameters in Migen like it : Instance("altera_pll", p_duty_cycle0=50, ...)
<FabM> Migen will generate verilog parameters like it : .duty_cycle0(6'd50), ...
<FabM> And value 6'd50 raise an error in Quartus synthesizer : Parameter "duty_cycle" of instance "general[0].gpll" has illegal value "110010"
<FabM> I managed to fix the error with top.v code following modification :
<FabM> .duty_cycle0(50), ...
<FabM> Is there an option in Migen to tell it not generating integer constant with size'dvalue, and just keep int value ?
<FabM> In fact I found the solution -> simply adding quote arround the integer parameter -> "50"
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<GitHub81> [artiq] sbourdeauducq pushed 5 new commits to master: https://git.io/vaHDl
<GitHub81> artiq/master 2cbe47e Sebastien Bourdeauducq: protocols/pc_rpc: document coroutine methods, support locking
<GitHub81> artiq/master 7657b67 Sebastien Bourdeauducq: devices/thorlabs_tcube: cleanup, convert to asyncserial
<GitHub81> artiq/master b5441fd Sebastien Bourdeauducq: devices/novatech409b: convert to asyncserial
<bb-m-labs> build #472 of artiq is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/472 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<rjo> FabM: ack. would be great if that could be added to the documentation.
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<FabM> rjo: I can do that
<FabM> rjo: In 'Instance' chapter ?
<FabM> doc/fhdl.rst
<rjo> FabM: yep. thx.
<GitHub38> [artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/vaHbM
<GitHub38> artiq/master 2bb4ad1 Sebastien Bourdeauducq: test: fix controller simulations
<sb0> does it print 50 in the verilog or "50"?
<FabM> sb0: it prints "50"
<FabM> sb0: but the error in quartus is disappear
<sb0> yes, so you're basically giving it a string value
<FabM> yes
<sb0> the acceptance of a string value where an integer is expected is an altera idiosyncrasy
<sb0> especially if an integer of another bit width doesn't work ...
<sb0> try Constant(50, 32)
<sb0> or Instance.PreformattedParam("50")
<FabM> Ok I try it
<rjo> PreformattedParam should be in the docs.
<FabM> Constant(50, 32) does'nt works : Error (14024): Parameter "duty_cycle" of instance "general[43].gpll" has illegal value "00000000000000000000000000110010" assigned to it. Possible parameter values are 1 to 99, inclusive. File: /opt/quartus/altera/15.1/quartus/libraries/megafunctions/altera_pll.v Line: 749
<rjo> i would guess that the bitwidth is not the problem here. altera docs don't even say what it is
<sb0> but verilog does. the default bit width of an integer constant is 32.
<FabM> It's ok with Instance.PreformattedParam("50")
<rjo> then probably altera only understands strings or literals.
<rjo> bitwidth-less literals
<FabM> But the verilog is generated with quotes "50" ...
<FabM> No
<FabM> In fact is generated without quote sorry
<FabM> Ok I'll change my platform code with Instance.PreformattedParam("50") then.
<larsc> if it is without any prefix it is a integer constant, isn't it?
<larsc> 110010 > 99
<sb0> Instance.PreformattedParam("50") should generate a verilog without quotes
<FabM> sb0: Yes it does
<bb-m-labs> build #473 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/473 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<sb0> the very purpose of Instance.PreformattedParam is to solve annoying synthesizers problems like that...
<sb0> hm I wouldn't put a PLL instantiation into the platform...
<FabM> sb0: The PLL is not instantiated in platform in fact. It's just a function we can call in our design to simplify this PLL instantiation.
<sb0> yes but you put that function into the platform
<FabM> because it's necessary if we wan't to use this clock with this fpga.
<sb0> there are many other situations where it is necessary to use some buffer to use a clock, e.g. for differential inputs
<sb0> if you look at those, the designs do not instantiate the differential input buffers in the platform either
<sb0> fpga clocking is complicated, and I don't think the platform can cover it
<sb0> the trivial clocks (a pin driving the clock directly) are fine, but everything else should be dealt with by the user
<FabM> Then you think the solution must be wrote in the design itself, not in a platform-function
<sb0> yes
<sb0> and/or some other library
<FabM> But in this case it's a «standard» solution to clock a simple design. I can put it in file apf6sp.py but not as method platform class ?
<sb0> maybe as a Module...
<FabM> because it's linked to this platform
<FabM> I added it as a inherit class from Module() -> class PciePllClockedModule(Module):
<sb0> ok
<FabM> New patch is coming
<FabM> I have a last problem with this platform : On apf6sp the cycloneV must be configured with bitstream in rbf format.
<FabM> And the build() method generate a .sof bitstream.
<FabM> To convert it I just have to launch the following command : os.system("quartus_cpf -c build/top.sof top.rbf")
<FabM> But this command should be in migen quartus platform I think
<sb0> _florent_, ^
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<FabM> _florent_: ok, but if we put that here the rbf will be generated each time we build for all altera platform
<FabM> I could add it if you want
<sb0> is that a problem? is it slow or anything?
<_florent_> if that's not long to generate I'm fine with that
<FabM> It take 5.8seconds on my computer
<_florent_> that's not long compare to P&R, so we can generate it each time, can you send a patch for that if you need it?
<FabM> Yes, patch is coming
<FabM> _florent_: done
<_florent_> ok thanks
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<GitHub43> [migen] enjoy-digital pushed 1 new commit to master: https://git.io/vaQEi
<GitHub43> migen/master 993ca00 Fabien Marteau: migen/build/altera/quartus.py: generating rbf bitstream format...
<FabM> thanks _florent_ ;)
<bb-m-labs> build #474 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/474
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