<whitequark>
with nothing. put a copy of crt0 there that points to separate main and isr inside the runtime
<whitequark>
then just put ex-ksupport code into the runtime
<sb0>
the idea of ksupport was to try to have a separate memory space for the kernel cpu, but that may not be necessary after all
<sb0>
(and never happened anyway)
<whitequark>
I mean, we already don't have a real separate memory space since the mailbox results in exchange of pointers
<sb0>
ok
<whitequark>
there are two issues with this plan
<whitequark>
1) it is mildly annoying to boot it
<sb0>
yes, but the comms CPU could have access to the kernel CPU memory space, but not vice-versa
<whitequark>
2) we need some way for code to tell whether it's running on kernel or comms CPU
<whitequark>
(could have access) I'm not so sure, e.g. how would the cache work?
<sb0>
the cpus have separate caches
<whitequark>
no
<sb0>
and you should flush them
<whitequark>
not the CPU cache
<whitequark>
the ARTIQ cache
<sb0>
put it in kernel CPU space
<sb0>
the comms CPU needs a relatively limited space for itself anyway doesn't it
<sb0>
?
<sb0>
couple megabytes at most
<whitequark>
that's an order of magnitude overestimated
<sb0>
yes
<sb0>
but still small compared to SDRAM size
<whitequark>
this reminds me, why is the comms CPU stack at the end of address space?
<whitequark>
I should select some 4M at the front and put comms everything there
<sb0>
for historical reasons I guess, misoc is doing that by default
<whitequark>
ah ok
<sb0>
anyway, I propose doing this cleanup/polishing after the rust runtime has feature parity with C + background RPCs are done
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<whitequark>
cleanup needs to wait until rust runtime is done anyway since I'm currently keeping the two in sync
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<cyrozap>
In Migen, is it possible to use a different clock domain for an FSM module than the default of "sys"? If not, am I using it incorrectly? I'm currently writing an I2C master module where I derive the I2C clock from the system clock and the I2C state machine should be using the I2C clock.
<sb0>
yes, use ClockDomainsRenamer
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<whitequark>
it kind of makes me sad that we can't run *only* Rust anywhere
<whitequark>
on comms CPU we're stuck with lwip, on kernel CPU we're stuck with libunwind
<whitequark>
although....
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<_florent_>
sb0/rjo: just a status on jesd: I'm still not able to get K28.5 (CGS) from the KC705 recognized by the AD9154
<_florent_>
sb0/rjo: my config is: 2Gbps line rate, 100MHz dacclk, 6Mhz sysref
<_florent_>
sb0/rjo: I'm working on it and I'm going to generate the jesd phy from the Xilinx wizard to see if there is some differences
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<rjo>
whitequark: are you in the lab by chance?
<rjo>
whitequark: if yes, or next time you get there, could you connect the second kc705 (with the dac fmc) to the network?
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<larsc>
_florent_: if the DAC is not seeing the CGS something is seriously wrong, probably at the lowest level. Maybe bit-order or incorrect clock settings
<rjo>
_florent_: that's without trying to use the ad9516's pll?
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<rjo>
_florent_: do the serdes plls lock?
<_florent_>
larsc: thanks, I'm going to verify with an oscilloscope that the transceiver is really outputing something (with slow pattern like 20 bits at 1/ 20 bits at 0)
<_florent_>
larsc: I checked bit order in simulation, maybe I have something wrong in the clock settings
<_florent_>
rjo: I'm not using the ad9516's pll, just feed the clock input of the ad9516 with a the user_sma clock of the KC705 and enable the dividers/outputs on the ad9516 like you are doing.
<_florent_>
rjo: no, I'm not able to get the lock on the serdes pll
<rjo>
_florent_: ok
<GitHub8>
artiq/phaser d2e9cf5 Robert Jordens: phaser: sync/sysref 33V banks
<GitHub8>
artiq/phaser ccf6a39 Robert Jordens: phaser: ttl channel for sync
<_florent_>
rjo: I found an initialization issue on the transceiver, they were not sending data, now it's fine (tested with a 20 bits to 1 / 20 bits to 0 pattern and an oscilloscope)
<_florent_>
rjo: now I'm pretty sure the K28.5 is sent correctly by the transceivers (simulated with xsim)
<_florent_>
rjo: but I'm still not able to get the SERDES PLL to lock and don't know why... (it should only depends of the clock input of the ad9154)