sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<jbqubit> ..
<rjo> howdy.
<jbqubit> boot log
<jbqubit> hody
<jbqubit> w
<rjo> ok. that looks good.
<rjo> note that there is no error in the startup_kernel.
<rjo> could you try dac_setup.py now?
<jbqubit> yes...
<rjo> i got two more minutes. then i'll have to leave for a while.
<jbqubit> refresh the gist
<jbqubit> for output of dac_setup.py
<jbqubit> ConnectionResetError: [Errno 104] Connection reset by peer
<rjo> that's new.
<rjo> and you definitely didn't change anything from when you first filed that issue report to now?
<rjo> your commands have shown three different outcomes so far.
<rjo> ip address is definitely that very board?
<jbqubit> Not true. I disconnected things to confirm stuff like phase lock of clocks. The reconnected .
<rjo> phase lock of which clocks?
<jbqubit> The KC705 responds to ping.
<rjo> sure. and there is exacly one kc705 on that network?
<jbqubit> 2 GHz clock to J1 and clock to KC705 on USER_CLK_N and _P.
<rjo> and there is exacly one kc705 on that network?
<rjo> jbqubit: you should not see anything on user_clk_n or p.
<jbqubit> 125 MHz to KC705
<rjo> anyway. gotta go. see you later.
<rjo> jbqubit: don't do that.
<jbqubit> I'm sending differential clock to KC705.
<rjo> why?
<rjo> it doesn't use that.
<jbqubit> Not sure if you're automatically switching to external clock.
<jbqubit> Based on previous system I expected FGPA clock and DAC clock needed to be phase synchronous
<rjo> don't assume things or speculate about how this works. it's not helpful.
<rjo> the fpga rtio clock is derived from the what the fpga gets from the clock distribution chip.
<jbqubit> Do FGPA clock and DAC clock need to be phase synchronous?
<rjo> there is no fpga clock.
<jbqubit> ok
<rjo> no clock coming from you anyway.
<rjo> anyway. gotta go.
<rjo> bbl
<jbqubit> OK. I'll be here if you're available after your dinner.
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<jbqubit> ok
<jbqubit> miraculously is started to work then stopped again
<rjo> exactly what worked?
<jbqubit> dac_setup.py
<jbqubit> test_ad9154_prbs.py
<jbqubit> test_ad9154_status.py
<jbqubit> test_ad9154_stpl.py failed
<rjo> jbqubit: please read the readme and observe the note on prbs testing.
<jbqubit> yes.
<rjo> are you trying to say you did that?
<rjo> and what does "stopped working" mean?
<jbqubit> the failures I observe are occasional. They include a) socket.timeout: timed out b) ConnectionResetError: [Errno 104] Connection reset by peer
<rjo> you will get an a) after each b) because you crashed the core device.
<jbqubit> OK
<rjo> i don't know how you do that. are you absolutely sure you used the correct toolchain to compile runtime, bios, startup_kernel, and the other kernels?
<rjo> how does _stpl fail.
<rjo> i.e. always be specific. "fail" is not something anyone can debugs. does it crash, does it say "FAIL"?
<jbqubit> You've already observed that I am capable of poor python library hygiene.
<rjo> well. which do you prefer: learn how to do it or receive instructions and follow them blindly?
<jbqubit> My understanding improves with our every interaction Robert.
<rjo> i will take that as a "neither" then ;)
<jbqubit> OK. Just rebooted the KC705. Then ran dac_setup.py. It was returned without error.
<jbqubit> What would you like me to try now.
<jbqubit> ?
<rjo> then run the demo.py and look at ch1 and ch2 on a scope
<jbqubit> running demo.py... it doesn't return... KC705 LEDs 4...7 are blinking at about 1 Hz
<rjo> i.e. keep demo.py running. it won't end by itself.
<jbqubit> No output on scope.
<rjo> all good.
<jbqubit> OK. What's next.
<rjo> ctrl-c on demo.py and run that *_status.py
<rjo> test_ad9154_status.py
<rjo> paste the output, preferrably _not_ in a comment on a gist.
<jbqubit> No output... ConnectionResetError
<jbqubit> $ artiq_run repository/test_ad9154_status.py Traceback (most recent call last): File "/home/britton/anaconda3/envs/artiq-phaser/bin/artiq_run", line 11, in <module> load_entry_point('artiq==3.0.dev0+159.gbf942fc.dirty', 'console_scripts', 'artiq_run')() File "/home/britton/artiq-dev-phaser/artiq/artiq/frontend/artiq_run.py", line 221, in main return run(with_file=True) File "/home/britton/artiq-dev-phaser/artiq/artiq/f
<rjo> yeah.
<rjo> don't pase that here!
<rjo> *paste
<jbqubit> You prefer pastepin?
<jbqubit> bin
<rjo> use pastebin, hastebin, a gist, anything.
<rjo> no. if the error is connetion reset, you need to restart, and run dac_setup.py again.
<rjo> then run *_status.py
<jbqubit> did reset
<jbqubit> but dac_setup.py fails with Connection reset by peer
<jbqubit> trying again
<jbqubit> now dac_setup.py returns
<jbqubit> _status successful
<jbqubit> creating gist
<rjo> that artiq/phaser commit that you are using is not the current one. it should not work.
<jbqubit> ommit bf942fc22858370dd378343aa5b36e6ec8fb39e6 Author: Robert Jordens <rj@m-labs.hk> Date: Tue Oct 18 11:37:27 2016 +0200 ksupport: adapt to dyld_load()
<jbqubit> is what I'm using
<rjo> good. run demo.py and look athe dac channels.
<rjo> yes. ok. that one should work.
<rjo> but do a git diff and paste the result. there should be only the ip change in device_db.pyon
<jbqubit> before proceeding please explain how I should interpert "that artiq/phaser commit that you are using is not the current one. it should not work."
<rjo> just did.
<rjo> there is one more current but that's irrelevant for this.
<jbqubit> OK
<jbqubit> Shall I get a fresh copy so it's clear that I've not broken anything?
<rjo> nah. lots of fallout from random edits. nothing substantial.
<rjo> to calm me down a bit could you "git checkout artiq/examples/phaser/repository/dac_setup.py"
<jbqubit> running demo.py
<rjo> yeah. and if you can. just take a photo of your setup (with the two boards and the cables). i'd like to have a look.
<jbqubit> LEDs 0...7 are 0001FFFF
<rjo> ?
<jbqubit> where F is flashing at ~ 1 Hz
<rjo> yes. that's good.
<rjo> 4-7 show the four jesd links clocking happily.
<rjo> 3 is "sync" which is if the dac has happily done cgs.
<rjo> what sma's do you have the scope connected to?
<jbqubit> sending photo of setup by email
<jbqubit> DAC0 DAC1 DAC2
<rjo> the have names starting with J
<jbqubit> J17, J4, J5
<jbqubit> and signal
<jbqubit> (photos sent via signal)
<rjo> ok. hmm.
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<rjo> jbqubit: set the scope to 50ns/div, channels to 100 mV/div and trigger on ch1 at 100 mV. but i don't think that's it,
<jbqubit> No that's not it.
<rjo> if that doesn't give you output, then i'd like you to try a bintstream/bios/runtime that we compiled: https://anaconda.org/m-labs/artiq-kc705-phaser/3.0.dev/download/noarch/artiq-kc705-phaser-3.0.dev-py_160+git062aca2.tar.bz2
<jbqubit> I reset KC705.
<jbqubit> Then ran dac_setup.py
<jbqubit> demo.py now produces output
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<jbqubit> nice
<rjo> ok. but you still have the crashes.
<jbqubit> It
<rjo> by the way. user_sma_n is used as an output (!). if you put stuff into there, i could imagine problems in the worst case.
<jbqubit> Yes. There are still many many crashes.
<rjo> good.
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<rjo> yeah. the crashes are not something i have seen ever.
<rjo> i'd still suspect a broken toolchain somewhere.
<rjo> if you get a crash, there should be something (that looks a bit like a windows bluescreen or linux kernel panic, i.e with hexadecimal numbers... on the console. please paste.
<jbqubit> Where should I be looking?
<rjo> for what?
<jbqubit> "if you get a crash..."
<rjo> "on the console" that's that flterm command
<jbqubit> OK
<jbqubit> Rebooting with flterm connection.
<rjo> do a "reboot, dac_setup.py, demo.py" iteration a few times.
<jbqubit> I observe Connection reset by peer error... but no output on serial port to flterm
<jbqubit> the last characters on serial connection are "Accepting network sessions."
<jbqubit> ping 192.168.1.71
<rjo> hmm. the comms cpu crashing hints to broken runtime. could you flash the three binaries from the conda package referenced above?
<jbqubit> gist on versions of conda and vivado... https://gist.github.com/jbqubit/e53449c1f522b43c665cda1ff47c9136
<jbqubit> Which conda package?
<rjo> see above.
<rjo> if that doesn't give you output, then i'd like you to try a bintstream/bios/runtime that we compiled: https://anaconda.org/m-labs/artiq-kc705-phaser/3.0.dev/download/noarch/artiq-kc705-phaser-3.0.dev-py_160+git062aca2.tar.bz2
<rjo> where is your llvmlite_artiq?
<jbqubit> I see.... downloading
<rjo> conda list is not conclusive because you can have stuff in ~/.local (as you have demonstrated)
<rjo> do a "which clang" and " python -c 'import llvmlite_artiq; print(llvmlite_artiq)'
<rjo> "
<rjo> i do appreciate the metric ruler in that photo. and the fact that you screwed the boards together.
<jbqubit> $ openocd -f board/kc705.cfg -c "init; jtagspi_init 0 bscan_spi_xc7k325t.bit; jtagspi_program top.bit 0x000000; jtagspi_program bios.bin 0xaf0000; jtagspi_program runtime.fbi 0xb00000; xc7_program xc7.tap; exit"
<jbqubit> Glad you appreciate those touches. :)
<rjo> yes. if you cd'ed deep into the unpacked package, that should work.
<jbqubit> Note that it's top.bin in the README_PHASER.rst
<rjo> oh. and don't be disturbed by the distortion on the scope for that demo output. that's due to the output transformers.
<rjo> yeah. you could have converted it with "python -m artiq.frontend.bit2bin top.bit top.bin" but it shouldn't matter much.
<rjo> iirc the fpga just ignores the header. if it fails to boot, you need to do the conversion.
<jbqubit> open ocd can't find board/kc705.cfg
<rjo> see the readme.
<jbqubit> OK... I remembering... I'm reading thatnow.
<rjo> you must have resolved this before.
<rjo> jmizrahi might be in the office/lab as well.
<jbqubit> $ openocd -s /home/britton/anaconda3/envs/artiq-phaser/share/openocd/scripts -c "init; jtagspi_init 0 bscan_spi_xc7k325t.bit; jtagspi_program top.bit 0x000000; jtagspi_program bios.bin 0xaf0000; jtagspi_program runtime.fbi 0xb00000; xc7_program xc7.tap; exit"
<jbqubit> I did resolve it last week.
<rjo> yeah looks ok. but while you are at it do the conversion.
<jbqubit> Error: Debug Adapter has to be specified, see "interface" command
<rjo> still needs -f board/kc705.cfg
<jbqubit> flashing
<rjo> ok. i have to go. let me kknow how you fare. i read the log. might be online intermittently while enroute.
<jbqubit> flashing finished
<jbqubit> reset board
<jbqubit> connection reset by peer...
<jbqubit> dac_setup.py ran
<jbqubit> dac_setup resulted in Connection reset by peer
<jbqubit> not better than my own
<jbqubit> $ artiq_run repository/dac_setup.py; artiq_run repository/demo.py
<jbqubit> is what I'm running after resetting board
<jbqubit> let "S" be I can successfully see waveform on scope; let "R" connection reset by peer
<jbqubit> RRRSRRRSSR
<jbqubit> In all cases I don't attempt artiq_run until "Accepting network sessions." appears on flterm
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<rjo2> and that's the only kc705 connected to that computer?
<rjo2> and you ran that git checkout command that I mentioned above?
<rjo2> and the two other commands above as well (clang and llvmlite artiq)
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<jbqubit> Yes.
<jbqubit> $ which clang ... /home/britton/anaconda3/envs/artiq-phaser/bin/clang
<jbqubit> $ python -c 'import llvmlite_artiq; print(llvmlite_artiq)' ... <module 'llvmlite_artiq' from '/home/britton/anaconda3/envs/artiq-phaser/lib/python3.5/site-packages/llvmlite_artiq/__init__.py'>
<jbqubit> I'm on a local subnet with only one kc705 attached.
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<rjo-> the llvmlite is suspicious. ist doesn't appear in your conda list output.
<rjo-> and the question is less about networking and not about whether you are flashing the right kc705.
<jbqubit> $ conda list llvmlite
<rjo-> and please paste a new boot console log from flterm.
<jbqubit> llvmlite-artiq 0.10.0.dev py35_24 m-labs/label/main
<rjo-> llvmlite_artiq that is.
<rjo-> Ok that llvmlite i
<rjo-> looks ok
<rjo-> clang as well
<jbqubit> Well, maybe I'm learning something.
<jbqubit> ;)
<rjo-> Ok. bitstream and bios and runtime good as well.
<rjo-> yep.
<rjo-> hmm. is there a switch between the kc705 and the computer?
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<rjo-> hmm. chances are slim that that's the problem.
<rjo-> you can try two things: either try the other kc705 that you have. or get rid of the switch. other than. those I don't see anything right now.
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<jbqubit_> ...
<rjo-> oh. and get a Paket dump from that connection reset.
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<jbqubit_> ok
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<jbqubit> wireshark dump sent
<jbqubit> by gmail
<rjo-> thanks.
<rjo-> jbqubit: will look at it tomorrow. gotta sign of now.
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<jbqubit> k