sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<cyrozap>
In a Migen FSM, what's the difference between "NextValue(foo, bar)" and "foo.eq(bar)"? Is it just for ease-of-reading or does it alter behavior?
<cyrozap>
Also, in simulation, my code seems to be hanging somewhere. Is there any way to probe to figure out where the hang is happening? The logic is not very complicated, and it's stalling within one clock cycle, so I'm not sure what's going wrong.
<cyrozap>
Oh, wow, those two questions ended up being related--changing my ".eq()"'s to NextValue's fixed the hanging issue.
<cyrozap>
Is there a way to set a custom timescale for a simulation?
<cyrozap>
Ah, found it.
<whitequark>
sb0: I just re-checked moninj again
<whitequark>
every TTL
<whitequark>
OE doesn't work on any single one...
<whitequark>
sb0: got your SFPs
<whitequark>
sb0: why is DMA base address 64-bit?..
<sb0>
whitequark, (moninj) ok, can you have a look at it?
<sb0>
(SFPs) thanks!
<sb0>
(DMA) for the analyzer I guess? let me check...
<whitequark>
the "byte count" seems to make sense, assuming it is never cleared
<whitequark>
base address though not so much
<sb0>
hm, how large is the KC705 memory again?
<whitequark>
1G I think
<whitequark>
I mean, it makes no sense given that mor1kx is 32-bit
<whitequark>
even if you could DMA beyond 4G I can't access it
<whitequark>
actually mor1kx might have a 64-bit option but the LLVM backend doesn't
<whitequark>
sb0: speaking of 64-bit stuff I've recently discovered that or1k has native 64-bit mul
<whitequark>
though it's sort of awkward
<sb0>
the root cause is misoc has a 30-bit memory address signal (in 64-bit words) for some reason
<whitequark>
should we add that, for faster RTIO math?
<whitequark>
ah
<sb0>
_florent_ did that port I think. maybe that's for supporting the larger SODIMMs?
<sb0>
ah, no
<sb0>
that's because it uses the default wishbone address size of 30 bits
<sb0>
which then gives you more than 2GB if the data width is >32
<sb0>
well, that's without serious consequences.
<whitequark>
yeah
<whitequark>
I noticed because rust has no implicit integer casts
<whitequark>
uuuugh
<whitequark>
Rust has no way to make an aligned struct
<sb0>
are you reading back OE immediately or with some delay? with the PHY readback it takes a bit of time for it to go through the CDCs so there's a race. it's unlikely the CPU will be that fast, but who knows
<whitequark>
with network delay
<whitequark>
I'm just waiting for the next Monitor request
<whitequark>
so a few millis
<sb0>
ok, that's definitely more than the CDC delay
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<GitHub194>
[artiq] whitequark pushed 1 new commit to master: https://git.io/vPG9R
<whitequark>
sb0: I can read back the O/OE/OVERRIDE_ENABLE values from injector
<whitequark>
let me look at the physical TTL no
<whitequark>
sb0: I'm confused. which LED on KC705 should RTIO channel 19 light up?
<whitequark>
GPIO_LEDS 2 ?
<whitequark>
that doesn't happen even from an experiment...
<whitequark>
and no, it doesn't happen if I do it via the injector
<whitequark>
so maybe RTIO is just broken?
<whitequark>
hm, no, this can't be, TestLoopback succeeds
<whitequark>
wtf
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<GitHub104>
[artiq] jordens pushed 6 new commits to phaser: https://git.io/vPZYW
<GitHub104>
artiq/phaser bd901e8 Robert Jordens: ad9154: status test
<GitHub104>
artiq/phaser 9771fb2 Robert Jordens: phaser: cleanup startup kernel
<GitHub104>
artiq/phaser 34b5227 Robert Jordens: ad9154_reg: portable helpers
<rjo>
vivado: INTERNAL ERROR on input pin '.:top/i_7:top__GCB7/I19[14]', trying to recover ...
<rjo>
i can't decide which makes me more uneasy. the fact that this smells like ICE or the fact that it even tries to recover from it...
<_florent_>
larsc: for jesd, I'm using the verilog scrambler you shared some time ago to check mine. But I'm simulating the Xilinx jesd core and the first scrambled data seem different (looking at the first datas just after ILAs and with input data =0). I'm trying to understand, maybe I'm doing something wrong in my simulation of the Xilinx core but I just want to know
<_florent_>
if I can use your verilog scrambler as a reference? Do you eventually have the first data outputed by the scrambler? (is it 0x0c000200, 0xf0002800, 0xc00c2002, 0x02ff802a, 0x280c0c02, 0x22f2f028, ...?)
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