sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> _florent_, what was the problem with https://github.com/m-labs/artiq/issues/312 ?
<sb0> the current code says:
<sb0> Keep(self.ethphy.crg.cd_eth_rx.clk)
<sb0> self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
<sb0> is that not reliable?
<sb0> and how is unreliable code more acceptable in artiq than misoc anyway?
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<nebarnix> Greetings!
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<larsc> rjo: if you split the trace on the pcb you'll get reflections
<larsc> if you hav a 1:2 chip it should be OK
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<rjo> larsc: ack. thanks.
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<key2> sb0: hi
<key2> sb0: what happened to this irq_ack in the misoc lib: https://github.com/m-labs/milkymist/blob/master/software/libbase/uart.c#L66
<key2> and I don't see where the IP (int pending) is cleared
<key2> and where does it clear the Interrupt Pending ?
<key2> should do a "wcsr IP, 1" or something similar
<key2> static inline void uart_ev_pending_write(unsigned char value) { MMPTR(0xe0001010) = value; }
<key2> but you see the ack used to happen here:
<key2> _florent_: the reason I am saying that is that I made a misoc/litex target in qemu, and when attaching gdb, I see that everytime, it gets back to the ISR because the IP is still saying that it's pending
<key2> so it looks like everytime an instruction is executed, we save all regs, go to isr, get out of isr, restore all regs, do a new instruction, and go back to interrupt....
<key2> because we never clear the IP
<_florent_> key2: not sure but maybe there is a mode for the interrupt (level or edge) and we are now using level mode(which means clearing the CSR clear the irq) and we were using edge in milkymist?
<_florent_> key2: and maybe the qemu is still using a edge mode
<key2> ah, that would make sense in this case
<key2> but what would set the ISR to be in level/edge mode ?
<key2> the config in the .v ?
<key2> or an instruction ?
<_florent_> yes maybe in config.v
<key2> don't see much in here
<key2> ahh
<key2> there we go
<key2> Enable level-sensitive interrupts. The interrupt line status is // reflected in the IP register, which is then read-only.
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<rjo> _florent_: i think we are missing input terminations on sysref and sync.
<_florent_> rjo: yes maybe, the initialization issue is probably around sysref/sync (terminations?, wait sysref edge to send start after sync is released?)
<rjo> _florent_: it could be a bouncy sync. i'll give it a shot.
<_florent_> rjo: can you check if sysref frequency is correct for my configuration: https://github.com/enjoy-digital/litejesd204b-ad9154-demo/blob/master/test/test_jesd.py#L35
<rjo> _florent_: (f_data*s)/(k*f)=15.625 MHz correct
<_florent_> rjo: ok thanks
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<_florent_> rjo: I was investigating the initialization problem but I stop for today. I stil don't understand.
<rjo> _florent_: ack.
<GitHub132> [artiq] jordens pushed 2 new commits to phaser: https://git.io/vXJSz
<GitHub132> artiq/phaser c428800 Robert Jordens: phaser: spi, sma_gpio: 2.5 V
<GitHub132> artiq/phaser 65b2e44 Robert Jordens: phaser: sysref/sync diff term
<rjo> _florent_: i now see about one failure (either SYNC low or no CGS) in 10 attempts.
<_florent_> rjo: ok and before it was something like 50% failure?
<rjo> _florent_: before meaning before your commits today. yes.
<rjo> _florent_: my commits, while correct, did not change that.
<_florent_> rjo: ok so at least it fixed something
<rjo> yes
<_florent_> rjo: a test we can do to be sure the transceiver are always initialized correctly is:
<_florent_> rjo: using the generate_square_wave signal
<_florent_> rjo: and do multiple initialization while looking at the lanes with a scope
<_florent_> rjo: but my scope is limited to 200MHz
<_florent_> rjo: and the signal will be 250MHz (10GHz/40)
<rjo> _florent_: hook it up to an ISERDES ;)
<_florent_> rjo: yes we could do that
<rjo> but you scope is probably -3 dB at 200 MHz not much worse than that at 250 MHz.
<_florent_> rjo: I'll do a test
<GitHub141> [migen] jordens pushed 1 new commit to master: https://git.io/vXJN1
<GitHub141> migen/master 73c607a Robert Jordens: build/tools: filter with line buffering
<bb-m-labs> build #102 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/102
<bb-m-labs> build #154 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/154
<bb-m-labs> build #135 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/135
<bb-m-labs> build #1029 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1029
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<rjo> whitequark: remind me: why did you roll back to llvm 3.8 for artiq?
<whitequark> rjo: there was a minor perf regression
<whitequark> and I didn't feel like figuring out the root cause at the moment, when I was upgrading LLVM for smething else entirey
<rjo> whitequark: ack.
<whitequark> rjo: do you need 3.9 for something?
<rjo> whitequark: no. just browsing the ecosystem.
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<whitequark> rjo: any answer from the picotcp folks?
<whitequark> re: LGPL relicensin
<rjo> whitequark: it looks like they won't do it.
<whitequark> rjo: ack
<whitequark> going to ask Brian to finish his cleanup work then
<rjo> whitequark: sounds good.
<rjo> whitequark: by the way. i had some weird "ConnectionClosed" events on the lab/kc705 combination today. maybe #456, maybe not. i couldn't reproduce them.
<whitequark> no pcap either I suppose?
<rjo> whitequark: no. will try to get one next time.
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