00:03 <sb0> context: wiki page about the spi servo

11:23 <GitHub199> [ionpak] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/ionpak/compare/ef52ca7e2cc9...914dc7f6c8f2

11:23 <GitHub199> ionpak/master 914dc7f Sebastien Bourdeauducq: increase clock frequency, enable FPU correctly

11:23 <GitHub199> ionpak/master 52c123f Sebastien Bourdeauducq: raise threshold for switching to more sensitive IC range

11:23 <GitHub199> ionpak/master 5f19c2f Sebastien Bourdeauducq: clean up gauge parameters

15:22 <key2> 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

15:26 <sb0> key2, ?

15:27 <key2> sorry

15:28 <larsc> political commentary about too many leading zeros?

15:40 <GitHub86> [artiq] jbqubit commented on issue #743: @jordens Do you have enough information to address this Issue? https://github.com/m-labs/artiq/issues/743#issuecomment-307828499

15:59 <GitHub176> [artiq] jordens commented on issue #743: Yes. https://github.com/m-labs/artiq/issues/743#issuecomment-307834308

17:10 <GitHub70> [artiq] jbqubit commented on issue #745: I don't want a beat between the DDS phase and the TTL pulse rising edge. ... https://github.com/m-labs/artiq/issues/745#issuecomment-307854229

17:23 <GitHub109> [artiq] sbourdeauducq commented on issue #745: So it works as expected? Can we close this? https://github.com/m-labs/artiq/issues/745#issuecomment-307857656

17:47 <GitHub27> [artiq] dleibrandt commented on issue #672: Just checked 2.3, and I still see the problem. https://github.com/m-labs/artiq/issues/672#issuecomment-307864632

18:00 <GitHub190> [artiq] sbourdeauducq commented on issue #672: Can you test with master, and post a minimal way to reproduce the problem? https://github.com/m-labs/artiq/issues/672#issuecomment-307868517

18:38 <GitHub128> [artiq] jordens pushed 6 new commits to master: https://github.com/m-labs/artiq/compare/566ff73dff6e...315338fca93f

18:38 <GitHub27> [artiq] jordens closed issue #743: sawg: clipping on phase jumps at large amplitudes https://github.com/m-labs/artiq/issues/743

18:38 <GitHub128> artiq/master 332bcc7 Robert Jordens: fir: check widths

18:38 <GitHub128> artiq/master 39a1dcb Robert Jordens: test/fir: look at overshoot behavior

18:38 <GitHub128> artiq/master 6ac9d0c Robert Jordens: fir/ParallelHBFUpsampler: add headroom (gain=2)...

18:43 <rjo> bb-m-labs: force build --props=package=artiq-kc705-phaser artiq-board

18:43 <bb-m-labs> build forced [ETA 13m46s]

18:43 <bb-m-labs> I'll give a shout when the build finishes

18:44 <bb-m-labs> build #1545 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1545 blamelist: Robert Jordens <rj@m-labs.hk>

18:46 <GitHub76> [artiq] jordens commented on issue #743: TL;DR: The FIR interpolator before the DUC overshoots. That is correct behavior.... https://github.com/m-labs/artiq/issues/743#issuecomment-307883024

19:03 <rjo> sb0: those lit tests also fail on my system.

19:10 <bb-m-labs> build #601 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/601

21:08 <GitHub126> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/e229edd5d554e637f2871371b99f658ddb62c030

21:08 <GitHub126> artiq/master e229edd Robert Jordens: sawg: add register after hbf for timing

21:09 <rjo> bb-m-labs: force build --props=package=artiq-kc705-phaser artiq-board

21:09 <bb-m-labs> build forced [ETA 13m46s]

21:09 <bb-m-labs> I'll give a shout when the build finishes

21:14 <GitHub191> [artiq] jbqubit commented on issue #745: OK. https://github.com/m-labs/artiq/issues/745#issuecomment-307931076

21:14 <GitHub104> [artiq] jbqubit closed issue #745: sawg: RTIO timing error between SAWG and TTLOut https://github.com/m-labs/artiq/issues/745

21:29 <GitHub196> [artiq] jordens commented on issue #745: If you don't want the beat, then reset the phase or choose a frequency that has zero beat. https://github.com/m-labs/artiq/issues/745#issuecomment-307934598

21:31 <GitHub136> [artiq] jbqubit opened issue #748: SWAG: phase offset between channels https://github.com/m-labs/artiq/issues/748

21:34 <bb-m-labs> build #1546 of artiq is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1546 blamelist: Robert Jordens <rj@m-labs.hk>

21:38 <GitHub175> [artiq] jbqubit opened issue #749: sawg: asymmetric sinusoid duty cycle https://github.com/m-labs/artiq/issues/749

21:42 <GitHub37> [artiq] jordens commented on issue #748: You are clearing the accu on one channel but not on the other. https://github.com/m-labs/artiq/issues/748#issuecomment-307937697

21:43 <GitHub107> [artiq] jordens commented on issue #748: You are clearing the accu on one channel but not on the other. https://github.com/m-labs/artiq/issues/748#issuecomment-307937697

21:50 <GitHub96> [artiq] jordens commented on issue #749: Duty cycle? You are running the DUC at 200 MHz frequency with a 300 MHz data rate, i.e. 100 MHz output as expected. The initial cycle is the AA filter trying its best to help you band-limit your signal. https://github.com/m-labs/artiq/issues/749#issuecomment-307940824

21:55 <GitHub48> [artiq] jbqubit commented on issue #748: > You are clearing the accu on one channel but not on the other.... https://github.com/m-labs/artiq/issues/748#issuecomment-307944061

22:06 <bb-m-labs> build #602 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/602

22:47 <GitHub38> [artiq] jbqubit commented on issue #749: By DUC I guess you mean digital up converter. ... https://github.com/m-labs/artiq/issues/749#issuecomment-307955945

22:56 <GitHub148> [artiq] jbqubit closed issue #749: sawg: asymmetric sinusoid duty cycle https://github.com/m-labs/artiq/issues/749

22:56 <GitHub193> [artiq] jbqubit commented on issue #749: The DAC_Filter_A filter in the Sinara repository is a single-pole Butterworth. Insertion loss is ... https://github.com/m-labs/artiq/issues/749#issuecomment-307958223