<sb0>
it seems only the beginning of the flash is written for some reason
<sb0>
the diffs between the .fbi and what is in the flash are in the strings that contain things that vary from compilation to compilation, like conda paths
<sb0>
the beginning, including the crc, is written correctly
<sb0>
openocd says "contents match", but when reading back the flash from the BIOS, they don't
<sb0>
bb-m-labs: force build --props=package=artiq-kc705-phaser artiq-board
<bb-m-labs>
build forced [ETA 12m09s]
<bb-m-labs>
I'll give a shout when the build finishes
<sb0>
oh, I found the bug
<sb0>
it's the conda binary patcher that helps itself with the .fbi file
<sb0>
I'm tempted to just encrypt it or something so that the conda garbage leaves it alone
<sb0>
oh versioneer has become fucked again, but only on the buildbot
<sb0>
Mismatch between gateware (3.0.dev+1126.g10fb6c62) and software (3.0.dev+1126.g10fb6c621) versions
<sb0>
non-reproducible by installing the conda packages locally
<GitHub11>
[smoltcp] whitequark pushed 1 new commit to master: https://git.io/vHbo1
<GitHub11>
smoltcp/master 80c20ad Egor Karavaev: Factor out the "raw_socket" and "tap_interface" features...
<GitHub57>
[smoltcp] whitequark closed pull request #15: Factor out the "raw_socket" and "tap_interface" features (master...split_std) https://git.io/vHF2d
<rjo>
i think vivado would duplicate registers itself
<rjo>
no
<sb0>
if there is no register to duplicate it cannot do anything
<sb0>
and register duplication only goes that far, in the end you have to distribute a signal to ~8ns across the entire chip. having slightly shifted reset regions is much more relaxed
<GitHub186>
[artiq] jbqubit commented on issue #751: OK. I see what's happening. The sawg configuration persists from one experiment to the next. Zeroing the other oscillator frequencies permits generation of the expected output. ... https://github.com/m-labs/artiq/issues/751#issuecomment-308856366