<GitHub3>
[artiq] jordens commented on issue #748: You can still use `with parallel`. Nobody is stopping you. And we generally try avoid describing all the things the API does not. Please file an issue if you are think the DDS docs are incomplete.... https://github.com/m-labs/artiq/issues/748#issuecomment-311588202
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<rjo>
cjbe (if you read this): thanks.
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<rjo>
sb0: are the cables from the AD9154 FMC to the scope the same length (to within 20 cm)?
<rjo>
_florent_: regarding the channel-to-channel latency difference (jesd204b, ad9154), you would expect that to be zero, right? the absolute latency is not deterministic but since they all go over the same link and they are still simultaneously aligned to each other, there would not be any latency offset between them.
<GitHub134>
[artiq] cjbe commented on issue #685: @whitequark using 3.0.dev+1186.gf36f00a8 I see a great improvement in speed for 'Transfer' (0.8 MB/s - 1.8 MB/s) but I still see 'Transfer' getting stuck sporadically (every 1-5 runs).... https://github.com/m-labs/artiq/issues/685#issuecomment-311617140
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<cr1901_modern>
Is the output of make_decoder supposed to be passed to a function that actually generates the expression used to select the region (like the old mem_decoder does)?
<cr1901_modern>
That was my follow up q. You plan to include that function in misoc too?
<sb0>
yes
<cr1901_modern>
The defaults have historically worked fine for me, but I can imagine users would want finer control over addr space usage (and to perhaps have RAM up to 2GB; I've never tried combining two 256MB regions w/ the default decoder tho)
<sb0>
they don't work for complex artiq drtio masters
<cr1901_modern>
why not (if you know)?
<sb0>
too many cores to map
<cr1901_modern>
Lastly, since I have some designs already; will I as a user have to provide the addr space from now on, or will a default be provided? If the latter will it be "the same" as the hardcoded decoder?
<cr1901_modern>
s/will it/will the default mapping/
<GitHub129>
[artiq] jordens commented on issue #761: Please refer to my comment above. I explained the first two cases. The line from SAWG has nothing to do with slack. "large enough slack" is un-knowable in `core.reset()` and `break_realtime()`. And having methods pre-compensate by adding slack for their own runtime would not be helpful. https://github.com/m-labs/artiq/issues/761#issuecomment-311729925
<rjo>
sb0: nice. reset_less signals really make a significant difference in phaser. about 15% fewer cells just from using them in the DSP part. having internal regs reset (implicitly) by the data pipeline is really nice.
<rjo>
and now it infers SRLs all over the place...
<rjo>
what i don't understand is why vivado infers 4 DSPs for the mor1kx 32x32 multiplier. since the output is only 32 bits, it can just drop the high mul. it doesn't signal overflows anyway. and also it seems to fail at pipelining that thing properly...
<rjo>
i suspect that might be a low hanging fruit and nice little project to educate/test people's skills on. or GSoC...
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<GitHub22>
[artiq] jordens commented on issue #762: The "decay" at the upper limit is the baluns highpassing your signal. When filing these bugs, please do have a look at the actual hardware you have in front of you, including cables, splitters, baluns, traces. A bit of diligence would make this debugging more efficient.... https://github.com/m-labs/artiq/issues/762#issuecomment-311749227
<_florent_>
rjo: about the channel-to-channel latency difference: yes I expect it to be zero, even if there is latency difference in the FPGA, the DAC is supposed to use the ILAS sequence to align channels
<rjo>
_florent_: that simulator that the lambda guys wrote, is that open? or did they just write the ethernet sim interface. it is a bit tricky to tell from the code...
<cr1901_modern>
Basically my question is: Can't resetless signals put your design in an invalid initial state _precisely_ because they have no reset? Reset-less signals will have to interface with other logic in your design that is subject to a reset signal.