sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<rjo> sb0: the command can be on a couple of things. i'll solve it with a bit of xdc magic because it gives a nice example of doing other things as well with those user-defined attributes.
<sb0> rjo, for SPI I'd have used the wishbone CSR generator and the misoc core to create the bus for the RTIO PHY
<sb0> now there are two different interfaces and code duplication...
<sb0> or even without the wishbone CSR generator - have your own SPI-core-specific CSR handler that packs the config CSRs into one single address
<sb0> why did you want to avoid the multiple config addresses that you'd get when using the misoc wishbone csr generator?
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<GitHub130> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/8399f8893df5b08528d4cfcfa57d00fe6f3452de
<GitHub130> artiq/master 8399f88 Sebastien Bourdeauducq: add kernel access to non-realtime SPI buses (#740)
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<bb-m-labs> build #625 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/625 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1561 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1561 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<rjo> sb0: splitting the registers on RTIO would have been too slow and inefficient.
<rjo> sb0: doing an RTIO event takes orders of magnitude longer than doing a non-RTIO bus access.
<rjo> i see the convenience of being able to use the autogenerated CSR stuff. but i don't like the speed penalty. an extension to AutoCSR that packs multiple CSRs into one address would be nice.
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<rjo> sb0: by the way, ASYNC_REG never got applied in the vivado AsyncResetSynchronizer.
<rjo> the wire gets the property, but the actual FFs don't.
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<sb0> rjo, does it matter for those settings registers?
<rjo> you tend to switch between devices and different xfer sizes/styles frequently.
<rjo> ultimately the idea of having profiles here would have been nice as well. then you don't have to manage the config/xfer switching in software at all.
<sb0> profiles including CS?
<rjo> sb0: yes.
<sb0> ok
<GitHub24> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/0d8067256bfcf0a370dbe0fe7fc2850a8077bbfb
<GitHub24> artiq/master 0d80672 Robert Jordens: rtio: refactor RelaxedAsyncResetSynchronizer
<bb-m-labs> build #626 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/626 blamelist: Robert Jordens <rj@m-labs.hk>
<bb-m-labs> build #1562 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1562 blamelist: Robert Jordens <rj@m-labs.hk>
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<GitHub69> [migen] jordens pushed 13 new commits to master: https://git.io/vHjTJ
<GitHub69> migen/master 11108cb Robert Jordens: xilinx: false_path the first register in AsyncResetSynchronizer...
<GitHub69> migen/master 1a5cdd5 Robert Jordens: vivado: save project
<GitHub69> migen/master 9cafae1 Robert Jordens: vivado: create project explicitly
<bb-m-labs> build #148 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/148
<GitHub181> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vHjTu
<GitHub181> migen/master c1da39d Robert Jordens: support reset-less Signals (closes #54)...
<bb-m-labs> build #149 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/149
<bb-m-labs> build #627 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/627
<bb-m-labs> build #628 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/628
<bb-m-labs> build #1563 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1563
<sb0> rjo, what is the typical frequency and voltage used in those ion traps that have large copper resonators?
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<rjo> sb0: depends on atom and trap size. anywhere between 5-200 MHz and 20-1000 V.
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