sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub102> [smoltcp] dlrobertson opened pull request #142: Add basic ICMPv6 reply (master...process_icmpv6) https://github.com/m-labs/smoltcp/pull/142
<sb0> _florent_, any comments/questions about the sc1 plan?
<GitHub162> [smoltcp] hjr3 commented on pull request #139 d006b48: sure, i wasn't trying not to hardcode the 2 https://github.com/m-labs/smoltcp/pull/139#discussion_r165551773
<GitHub74> [smoltcp] hjr3 commented on pull request #139 24e9948: ah, i can just use `field::OPTIONS(self.length).end` as it already contains the `+ 2` offset. https://github.com/m-labs/smoltcp/pull/139#discussion_r165552350
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<GitHub101> [smoltcp] dlrobertson commented on pull request #139 24e9948: Can be condensed to... https://github.com/m-labs/smoltcp/pull/139#discussion_r165553532
<GitHub25> [smoltcp] hjr3 commented on pull request #139 c6dc8ab: fixed https://github.com/m-labs/smoltcp/pull/139#discussion_r165554023
<GitHub66> [artiq] jbqubit commented on issue #911: So I updated Misoc and the error is still there...... https://github.com/m-labs/artiq/issues/911#issuecomment-362481490
<GitHub135> [artiq] sbourdeauducq commented on issue #911: Use the latest misoc from git (conda package probably available still, or you can trigger a build on Irc) we're not doing ci and full conda support for Sayma yet. https://github.com/m-labs/artiq/issues/911#issuecomment-362487333
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<GitHub51> [artiq] whitequark commented on issue #911: @jbqubit Did you run `git submodule update --init` in the misoc checkout? https://github.com/m-labs/artiq/issues/911#issuecomment-362504743
<GitHub190> [artiq] whitequark commented on issue #911: @jbqubit Did you run `git submodule update --init` in the misoc checkout?... https://github.com/m-labs/artiq/issues/911#issuecomment-362504743
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<GitHub191> [smoltcp] batonius commented on pull request #142 e087075: Unrelated to the PR, but do we really need to clone `self.device_capabilities.checksum` everywhere? https://github.com/m-labs/smoltcp/pull/142#discussion_r165590027
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<_florent_> sb0: yes sc1 plan seems clear, i'm working on that
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<_florent_> sb0: it seems i'm not able to get a console on sayma3, i'm able to flash it, restart it but then nothing in flterm...
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<_florent_> sb0: i've been able to test on my kcu105 + AD9154 that the DAC seems to be working in subclass 1
<_florent_> sb0: i verify that we receive the sysref (SYNCARM should be low)
<_florent_> sb0: and that the phase error is within the tolerance (SYNC_WLIM should be low)
<_florent_> sb0: i added these checks, no i wanted to test on sayma and add delay on the sysref, but i'll do that another day if sayma3 is not working
<_florent_> no i / now i
<sb0> _florent_, sayma3 should be working
<_florent_> sb0: i'm not able to get something on flterm
<sb0> sigh
<sb0> did jtag work?
<_florent_> sb0: yes
<sb0> it detected both fpgas?
<sb0> what port are you using for serial?
<_florent_> flterm /dev/ttyUSB_sayma-3_0
<sb0> did you try multiple times?
<_florent_> yes
<sb0> how did you load the fpga?
<_florent_> ./artiq_flash.py -t sayma --srcbuild artiq_sayma --preinit-command "ftdi_location 5:1"
<sb0> boot is rather slow, did you wait long enough?
<_florent_> i think... 20 minutes would be really slow... :)
<sb0> are you using the board right now or can I try?
<sb0> geez those sayma are such a pain in the ass
<_florent_> i was going to ask you to try if possible
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<sb0> _florent_, okay, for some reason this shitty FPGA isn't reading its flash to get the bitstream; loading the .bit manually from JTAG works around the problem
<sb0> (or the bitstream wasn't correctly loaded in the flash)
<_florent_> sb0: hmm ok, can you eventually try to flash a bistream? (it could also be my bistream that is not working, but i don't know why it would be the case...)
<sb0> okay, flashing now ...
<sb0> I assumed you did those tests
<sb0> _florent_, what allowable error window did you program into the DAC?
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<sb0> if we want to check sysref s/h, that error window should be zero
<sb0> did you scan the sysref phase and found phases for which REF_WLIM was set, indicating phase error outside the window?
<sb0> _florent_, sayma-3 boots just fine when I flash it
<_florent_> sb0: hmm
<sb0> it even talks with sayma-1 with drtio
<_florent_> sb0: can i try?
<_florent_> sb0: for flashing, you are using the same command i use?
<sb0> _florent_, ok I unlocked the board
<sb0> open a terminal and do artiq_flash start. you should see the boot
<_florent_> yes i'm doing that
<sb0> my command was "artiq_flash.py -t sayma --srcbuild bin_satellite --preinit-command "ftdi_location 5:1" -V satellite", which is equivalent to yours
<_florent_> ok i see the boot
<_florent_> let's try to reflash my bistream
<sb0> you can just load it
<sb0> no need to flash
<sb0> it's faster
<sb0> unless you want to run your modified runtime too
<_florent_> sb0: yes i'm setting the window to the minimum (1/2 DAC clk) and want to scan sysref with REF_WLIM
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<_florent_> sb0: stilll not able to get my bistream working (by flashing or loading), i'll regenerate it...
<_florent_> sb0: thanks for testing
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<GitHub26> [artiq] hartytp commented on issue #854: @gkasprow can you ping your board?... https://github.com/m-labs/artiq/issues/854#issuecomment-362615001
<GitHub14> [artiq] hartytp commented on issue #854: Oops, presumably Greg's test wasn't done with Artiq. That should be the next step, I guess... https://github.com/m-labs/artiq/issues/854#issuecomment-362616089
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<hartytp> sb0: I've lost track, but what's breaking memtest on Sayma?
<hartytp> this was working before, but I put a more recent version of ARTIQ on and I'm now getting errors
<sb0> hartytp, we didn't find out why
<sb0> ah interesting
<sb0> maybe it works on mine with the latest version because I had disabled many peripherals for the ethernet tests
<sb0> and it's either vivado timing nondeterminism or plain miscompilations
<hartytp> vivado is 2017.4
<hartytp> will try rebuilding with python -m artiq.gateware.targets.sayma_amc --without-sawg
<hartytp> anyway, I this error is new and not something I'd seen before
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<hartytp> hmm now nothing on the UART at all...will pick this up again on Monday
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<_florent_> hartytp: hmm that's maybe the same issue i have...
<GitHub7> [artiq] jbqubit commented on issue #911: > we're not doing ci and full conda support for Sayma yet.... https://github.com/m-labs/artiq/issues/911#issuecomment-362648668
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<GitHub154> [artiq] sbourdeauducq commented on issue #911: Try using the conda packages. https://anaconda.org/m-labs/misoc/files is up to date. https://github.com/m-labs/artiq/issues/911#issuecomment-362656022
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<GitHub167> [smoltcp] AdamNiederer commented on issue #100: I'm seeing a 2x speedup on AVX with `faster`, and a 20-40% speedup on SSE using an unreleased verison of `faster`. I'll send a PR once 0.5.0 is out. https://github.com/m-labs/smoltcp/pull/100#issuecomment-362679056
<GitHub190> [smoltcp] AdamNiederer commented on issue #100: I'm seeing a 2x speedup vs. this PR on AVX with `faster`, and a 20-40% speedup on SSE using an unreleased verison of `faster`. I'll send a PR once 0.5.0 is out. https://github.com/m-labs/smoltcp/pull/100#issuecomment-362679056
<GitHub51> [smoltcp] AdamNiederer commented on issue #100: I'm seeing a 2x speedup vs. this PR on AVX, and a 20-40% speedup on SSE using an unreleased verison of `faster`. I'll send a PR once 0.5.0 is out. https://github.com/m-labs/smoltcp/pull/100#issuecomment-362679056
<GitHub37> [artiq] gkasprow commented on issue #854: I will test it with board @sbourdeauducq sent to me. Will try it with Artiq and on my setup. https://github.com/m-labs/artiq/issues/854#issuecomment-362711058
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<GitHub147> [artiq] hartytp commented on issue #854: Thanks Greg! https://github.com/m-labs/artiq/issues/854#issuecomment-362720836
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<GitHub172> [smoltcp] LuoZijun opened pull request #143: Imp `From` trait on EthernetAddress (master...patch-7) https://github.com/m-labs/smoltcp/pull/143
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<GitHub39> [artiq] whitequark commented on issue #911: > @whitequark I cloned with --recursive.... https://github.com/m-labs/artiq/issues/911#issuecomment-362732166
<GitHub71> [smoltcp] whitequark commented on issue #143: Why? https://github.com/m-labs/smoltcp/pull/143#issuecomment-362734915
<GitHub197> [smoltcp] whitequark commented on pull request #142 e087075: Borrow checker and closures. https://github.com/m-labs/smoltcp/pull/142#discussion_r165790079