<GitHub15>
[smoltcp] whitequark commented on issue #147: The standard library types have a different API that doesn't follow the way every other type in smoltcp is designed. Read the documentation for the wire module to see what I mean. https://github.com/m-labs/smoltcp/issues/147#issuecomment-363034591
<GitHub50>
[smoltcp] dlrobertson commented on issue #142: I realize now I could have broken this PR up into two parts. If it makes it easier to review, I can submit a PR for the work in `wire` then a PR for the work in `iface`. https://github.com/m-labs/smoltcp/pull/142#issuecomment-363061995
<GitHub27>
[smoltcp] dlrobertson commented on issue #142: I realize now I could have broken this PR up into two parts. If it makes it easier to review, I can submit a PR for the work in `wire` then a PR for the work in `iface`. If this is preferred, just let me know. https://github.com/m-labs/smoltcp/pull/142#issuecomment-363061995
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<GitHub169>
artiq/master e50bebb Florent Kermarrec: firmware/liboard_artiq/ad9154.rs: add checks for jesd subclass 1 (verify that we receive the sysref and that phase error is within the specified window error threshold).
<GitHub169>
artiq/master e80b481 Florent Kermarrec: firmware/libboard_artiq/hmc830_7043.rs: add template for sys_ref phase configuration for dac1/dac2 and fpga
<bb-m-labs>
build #2031 of artiq is complete: Failure [failed python_coverage_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2031 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<_florent_>
sb0: i added jesd sc1 checks in the artiq firmware. For now i'm not able to implement the algo you described since i'm not able to see that sys_ref clock is delayed when i configure the delay on the hmc7043 (i'm looking at REF_WLIM / CURRERR / LASTERR bits of AD9154 but i'm not able to notice changes)
<_florent_>
sb0: the AD9154 reports REF_WLIM = 0, so jesd sc1 should be fine, but i'd like to increase sys_ref delay and have REF_WLIM=1 to be sure everything is working correctly
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<larsc>
you set the window to +-1/2 clock cycle and then check wlim?
<_florent_>
sb0: at least i know that the DAC is taking sysref into account: if i disable sysref on the hmd7043, SYNCARM is still at 1 and LASTERR is 0
<larsc>
_florent_: only fine delay or also coarse delay?
<_florent_>
sb0: when i enable sysref, SYNCARM is at 0 and LASTERR has a value
<_florent_>
larsc: i tried both, but i don't see CURRERR or LASTERR changing when doing that
<_florent_>
larsc: we are using syncmode = 0x9, so i tried monitoring CURRERR and changing the delay, but CURRERR was not changing
<GitHub157>
[artiq] whitequark commented on issue #915: @jordens I don't remember the exact diff between 2.27 and 2.25.1. I think 2.27 is just 2.25.1 plus our patches. The Windows build requires Cygwin and that isn't currently automated. https://github.com/m-labs/artiq/issues/915#issuecomment-363185972
<GitHub10>
[artiq] gkasprow commented on issue #854: I'm waiting for AMC board to arrive from customs. Unfortunately the tracking number is not enough to get any info about it since there are many customs agencies in Warsaw.... https://github.com/m-labs/artiq/issues/854#issuecomment-363241598
<GitHub37>
[artiq] gkasprow commented on issue #854: @sbourdeauducq did you send it by standard post? Polish post office does not register international parcels so you cannot track them in Poland. And it's quite common to wait 2 weeks for delivery. https://github.com/m-labs/artiq/issues/854#issuecomment-363245036