sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub143>
[artiq] whitequark commented on issue #908: The boot messages are displayed by the `read_bitslip` and `read_delays` functions. Memory check likely fails because write leveling exists for a reason. https://github.com/m-labs/artiq/issues/908#issuecomment-366833431
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<sb0>
whitequark, any update on the camera driver?
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<whitequark>
no. I've been looking into the buildbot breakage
<sb0>
windows python?
<whitequark>
yes, and other issues too
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<GitHub49>
[artiq] sbourdeauducq commented on issue #902: @jonaskeller How are things (flashing and panic) with a recent artiq-4 package from master? If everything works I'll backport the changes to release-3 and make a new release. https://github.com/m-labs/artiq/issues/902#issuecomment-366895441
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<sb0>
rjo, FYI I'm going to order another kasli for m-labs hk, it's definitely more pleasant to debug/develop drtio there than on kc705 (transceiver bugs) or sayma (no comment), and one of the two kasli we have atm will go to china soon
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<sb0>
those transceivers also seem to guzzle power. heat-sinked FPGA is at 71C with ethernet and drtio running...
<rjo>
sb0: ack. it's a really nice board.
<rjo>
sb0: be careful with esd though (i2c switch seems sensitive) and i put a 25x25mm 12v fan onto the heat sink. with opticlock it's now at 48c. the amount of LVDS buffers is driving power usage.
<rjo>
sb0: care to do a quick code review of the new spi core?
<GitHub121>
misoc/spi2 e79ea98 Robert Jordens: spi2: new spi master core...
<rjo>
sb0: i'll stage that without disturbing the old core and then transition the upper layers one by one.
<sb0>
rjo, is the oxford ad9910 support complete with the current code?
<rjo>
documentation still. and i couldn't get it to work at full speed yet (62.5 MHz SPI clock) which bothers me. and it doesn't initialize and lock the plls correctly from time to time.
<GitHub10>
artiq/master 7d9c7ad Sebastien Bourdeauducq: drtio: fix test infinite loop
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<GitHub59>
[artiq] hartytp commented on issue #908: @enjoy-digital did you have a chance to fix the timing issues with serwb that @sbourdeauducq mentioned? I know that these are unlikely to be the cause of the SDRAM issues, but it's probably a good idea to mop up all the known issues as a starting point to fixing this.... https://github.com/m-labs/artiq/issues/908#issuecomment-366926989
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<hartytp>
rj0: do you have a pair of a Kasli with DRTIO working? If so, would you be interested in doing a phase stability measurement at some point soon? Idea would be to put the output of the Si5324 clocks onto a 2-channel ADC and do a long-term (hours) phase drift measurement
<hartytp>
let the DRTIO master free-run and compare the phase wander of the locked slave DRTIO clock relative to the master
<GitHub111>
[artiq] gkasprow commented on issue #854: OK, so first I will fix the PAUSE issue to make it working with other media converters. If you want me to look at the PHY signals I can do that - I have low capacitance (<1pf, 1.5GHz) active probes and can observe 4 signals at a time or 8 using 2 scopes. https://github.com/m-labs/artiq/issues/854#issuecomment-366937589
<_florent_>
sb0: do you have a bistream where ddr3 fails on sayma3? I'd like to do some tests
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<sb0>
marbler, I have many times of sot23 mosfets but iirc no LEDs
<sb0>
well, there are probably SMD LEDs to be scavenged from one of the electronics trash boxes
<sb0>
*many types
<sb0>
_florent_, I don't... and whether it fails or not depends on the board
<sb0>
_florent_, you can look at the issue (I posted a few binaries)
<GitHub107>
[artiq] enjoy-digital commented on issue #908: I'd like to see if it's an issue with the read leveling algorithm or something else, but i'm not able to reproduce the issue on the HK boards. Can someone that is able to reproduce the issue apply this patch: https://hastebin.com/akoketutut.swift, rebuild the bootloader (use --no-compile-gateware), re-flash the bootloader (artiq_flash ... bootloader) and post the result
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<GitHub122>
[sinara] gkasprow pushed 1 new commit to master: https://git.io/vARzp
<GitHub122>
sinara/master 8004bee Greg: added panel design for Grabber
<GitHub169>
[artiq] enjoy-digital commented on issue #908: @hartytp: yes that's what i want, please also use write_leveling. (you can also test with deadzone of 16, 32 and then the patched version). ... https://github.com/m-labs/artiq/issues/908#issuecomment-367029929
<GitHub193>
[artiq] jonaskeller commented on issue #902: Conda still defaults to `4.0.dev-py_206+git70130847` for the `artiq-kc705-nist_qc2` package. If I try to force either `py_553+git07a31f8d` or `py_582+gitf060d6e1`, it complains about not being able to fulfill the `openocd 0.10.0 4` dependency. https://github.com/m-labs/artiq/issues/902#issuecomment-367074931
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