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<GitHub34>
[smoltcp] canndrew commented on issue #156: I don't know why you're being so needlessly hostile. Most of your complaints so far make no sense, but I've ignored them because they're irrelevant anyway.... https://github.com/m-labs/smoltcp/issues/156#issuecomment-365175541
<sb0>
what, xc3sprog found the jtag cable that just arrived in the mail and then the urukul cpld, with just one package installation and the documented detection command?
* sb0
goes buy lottery tickets
<sb0>
rjo, what is the simplest way to clock urukul?
<sb0>
it doesn't even take 30min to compile, amazing
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<sb0>
okay, this makes DRTIO meet timing at 150MHz on Kasli
<sb0>
I wonder why Xilinx block RAMs are so slow. inside Intel CPUs there are larger RAMs for things like L1 caches and they're clocked at GHz rates ...
<larsc>
if nothing else in the fabric can run that fast no need to invest resources in faster memory
<larsc>
ultrascale as ultraram, btw
<larsc>
I think it is faster
<larsc>
altera startix10 has hyperregisters, I wonder whats next after ultra and hyper
<sb0>
still, the clock-to-out delay of BRAM is pretty bad
<larsc>
that's why you have the built-in pipelining register
<sb0>
it doesn't really work :) on many Xilinx FPGAs it still gives much worse timing than a fabric register connected to the block RAM output
<GitHub157>
artiq/master df177bf Sebastien Bourdeauducq: use new misoc identifier
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<GitHub81>
[smoltcp] le-jzr commented on issue #156: @canndrew You could just define the wrapper type in your user code. I get that your intention is to make smoltcp better according to you own personal preferences, but those don't match the design decisions behind this crate. @whitequark is entirely justified in telling you that you are trying to use the type for something it's not intended for. Yes, you can support all the pos