sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<mithro> whitequark: Does https://github.com/YosysHQ/yosys/pull/905 help with nMigen in any way?
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<mtrbot-ml> [mattermost] <joeshardow> joeshardow joined the team.
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<whitequark> mithro: not really, because yosys is calling python there, not the other way around
<whitequark> it'd have to be "libyosys", but in any case that's a horrible pain on windows...
<mtrbot-ml> [mattermost] <sb10q> whitequark: any issues with making it WSL-only?
<mtrbot-ml> [mattermost] <sb10q> can vivado etc. be invoked from WSL?
<whitequark> sb10q: mattermost breaks nickname completion, which is extremely obnoxious.
<whitequark> as for making it WSL-only, yes, Windows should be a first-class platform and there's no reason to not do so
<whitequark> what I mean is, libyosys doesn't exist in the first place (not with Python bindings, anyway), there's no point in writing it, and doing so would make it more annoying to use nmigen on Windows
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<ZirconiumX> So, in Migen you would inherit from Module and do your logic in __init__, but in nMigen you put the logic in an elaborate() function?
<ZirconiumX> Also, in terms of writing a boring adder, is it better to use `+` or write your own?
<mtrbot-ml> [mattermost] <sb10q> ZirconiumX: yes, your class doesn't have to derive from anything with nMigen
<mtrbot-ml> [mattermost] <sb10q> why would you write your own adder?
<ZirconiumX> To learn how to write an adder, I suppose
<mtrbot-ml> [mattermost] <sb10q> FPGAs have dedicated structures for adders that you want to use for efficiency reasons
<mtrbot-ml> [mattermost] <sb10q> so... writing an adder isn't as simple as you may think
<ZirconiumX> That's useful to know at least
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<ZirconiumX> Um.
<ZirconiumX> I think I broke nmigen
<whitequark> sb: ^ and here we have a nice demonstration of why all python functions should check argument types.
<whitequark> you're welcome to figure out where that bool value comes...
<ZirconiumX> I can post my source if you want?
<whitequark> sure
<ZirconiumX> Actually, I think I know what it might be
<ZirconiumX> Can nmigen synthesise comparison?
<whitequark> of course
<ZirconiumX> Hmmm, I thought it was line 47 that might cause it, but replacing the comparison with an addition produces the same error
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<ZirconiumX> The bug disappears when you comment line 71, 80 and 81
<ZirconiumX> Uncommenting any one of those lines causes the bug to reappear
<whitequark> 81 is a brace ]
<whitequark> oh yeah
<whitequark> it should be ((width, True))
<ZirconiumX> Well, we found a bug in both my code and yours :P
<whitequark> it's not a bug in my code
<ZirconiumX> Bad error message, then.
<whitequark> nah
<whitequark> it's a bug in python. the bug is that it doesn't have a typechecker.
<ZirconiumX> Well, you could always use operator overloading in C++ :^)
<whitequark> that's completely irrelevant
<ZirconiumX> I was joking, don't worry
<_whitenotifier-1> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fjIyF
<_whitenotifier-1> [m-labs/nmigen] whitequark a74cacd - hdl.ast: handle a common typo, such as Signal(1, True).
<whitequark> should fix it
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<_whitenotifier-1> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/515246413?utm_source=github_status&utm_medium=notification
<_whitenotifier-1> [nmigen] jfng synchronize pull request #46: [WIP] Add nmigen.build - https://git.io/fjfqY
<_whitenotifier-1> [nmigen] jfng commented on pull request #46: [WIP] Add nmigen.build - https://git.io/fjISZ
<_whitenotifier-1> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/515254572?utm_source=github_status&utm_medium=notification
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<ZirconiumX> Is Migen's `>>` operator arithmetic or logical?
<whitequark> arithmetic in nmigen
<ZirconiumX> So how do I do logical shift?
<ZirconiumX> *logical right shift
<whitequark> signals are unsigned by default
<whitequark> so arithmetic and logical are the same
<ZirconiumX> So to get an arithmetic shift I use a signed signal and to get a logical shift I use an unsigned signal?
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<whitequark> yeah
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<vup2> whitequark: is it possible in nmigen to prevent undriven signals from becoming ports?
<whitequark> vup2: #30
<whitequark> i really need to fix this, it's one of the worst issues currently
<whitequark> and i will
<vup2> ah, sorry should have looked at the open issues list more carefully
<whitequark> it's okay
<vup2> well thank you anyways
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