sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<mtrbot-ml> [mattermost] <sb10q> @astro regarding test environment variables
<mtrbot-ml> [mattermost] <sb10q> see here https://m-labs.hk/artiq/manual-master/faq.html#run-unit-tests
<mtrbot-ml> [mattermost] <sb10q> there might be some inaccuracies, please fix them if you find any
<mtrbot-ml> [mattermost] <sb10q> there's also the ARTIQ_LOW_LATENCY variable that enable tests that are impacted by network latency
<mtrbot-ml> [mattermost] <sb10q> does your windows VM have access to the network to talk to the core device?
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<travis-ci> jhwgh1968/smoltcp#1 (fuzz_injector - 5f56d66 : jhwgh1968): The build passed.
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<kc5tja> Hello all. I have an nmigen question, about how to factor common tasks in test-cases. Can someone show me an example test case class where, for example, a bus transaction is factored out?
<whitequark> take a look at the FIFO classes
<whitequark> they have a read() method you can call with `yield from fifo.read()`
<kc5tja> In the body of a process procedure, I know that yield is used to 'return' the steps for the simulator to execute (e.g., yield foo.my_signal.eq(0)), but when this compounds, things get very confusing very fast.
<kc5tja> Sweet, thanks!!
<whitequark> there's a flaw in them in that they can't be easily parallelized
<mtrbot-ml> [mattermost] <sb10q> tried building another lineageos variant. this time it ran for 45min, and then the JVM segfaulted :)
<mtrbot-ml> [mattermost] <sb10q> https://hastebin.com/yosamigefe.shell
<mtrbot-ml> [mattermost] <sb10q> seriously, android is even worse than FPGA
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<_whitenotifier-1> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fjtj3
<_whitenotifier-1> [m-labs/nmigen] whitequark 49eef77 - hdl: remove deprecated get_fragment() and lower() methods.