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<sb0>
what's yumewatari?
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<sb0>
hmm 5gpbps...
<whitequark>
sb0: my pcie phy
<whitequark>
unfinished, pending nmigen
<sb0>
no SFP on devboard?
<whitequark>
only gbe
<whitequark>
there are SMAs though for the other SERDES
<sb0>
yeah but I don't want to make an adapter
<lkcl>
whitequark: i've done python module import-walking a number of times.
<lkcl>
i'll try to recall how it's done.
<lkcl>
imputil
<whitequark>
sb0: the other board *only* has a shitton of SMAs
<whitequark>
and it's completely useless
<lkcl>
sb0: "replace the python site packages path with <site-packages>" - ringing alarm bells at that
<whitequark>
sb0: maybe it's possible to halfass the connector? rip apart the SMA pigtail and solder it right onto the module
<sb0>
yeah, sure, but it's messy and fragile
<sb0>
and you need to power the module etc.
<sb0>
I don't get that other devkit indeed. and it has 2.54mm prototyping areas?
<sb0>
no sdram
<lkcl>
whitequark: i believe imputil will be a good place to start. damn it was only 8 months ago i did some *really* extensive python-module introspection... trouble was, the project was such hell, i was treated so badly that i've mentally erased the incident.
<lkcl>
you can i believe get at object.__module__
<sb0>
so you can add DIP chips?
<lkcl>
it's hidden
<lkcl>
ah, no, here you go:
<lkcl>
>>> x = 5
<lkcl>
>>> x.__class__.__module__
<lkcl>
'__builtin__'
<sb0>
lkcl: iirc that only gives you the top-level name of the module and not its path
<lkcl>
sb0: that's what imputil is for
<lkcl>
i've had to deal with this extensively, three times in 20 years of working with python
<lkcl>
it'll just take me a while to drag it out of my long-term chemical memory
<whitequark>
sb0: it doesn't even have a crystal
<whitequark>
completely pointless stupid devkit
<whitequark>
lattice has devkits like that, there's the "UPduino" with what we call a "scenic route ground trace"
<lkcl>
>>> x = Signal()
<whitequark>
routed by some kid in sri lanka or something
<lkcl>
>>> x.__class__.__module__
<lkcl>
'nmigen.hdl.ast'
<whitequark>
completely nonfunctional pll
<sb0>
you can add a CMOS oscillator like in 80s-era computers on the protoyping area :)
<whitequark>
lol
<whitequark>
i think you can make an inverter inside the FPGA and run the xtal like that
<sb0>
though I'm not sure if they're even available in 3.3V
<whitequark>
i never tried it
<whitequark>
i should, always been curious
<sb0>
there are some old CPLD appnotes that say you can do that
<whitequark>
i know for a fact that xtal driver chips are just four inverters
<whitequark>
1 inverter to actually oscillate, 3 more to clean up the output
<whitequark>
to get rail to rail waveform
<sb0>
4 inverters don't invert, no?
<whitequark>
one inverter connected across xtal
<sb0>
ah ok
<whitequark>
other three in a chain connected to output of 1st one
<whitequark>
sometimes you get two if the vendor is a cheapass
<whitequark>
the versa devkit is weird too
<whitequark>
it has the ecp5 and also it has an ispclock chip
<lkcl>
what the hell is the Zynq ZC706 USD $2500 for??? :)
<lkcl>
whitequark, sb0: you got all that voodoo magic? os.path.abspath(sys.modules[an_instance.__class__.__module__].__file__)
<whitequark>
that's not actually applicable
<lkcl>
that'll give the full absolute path of the module that any given object instance comes from
<lkcl>
what's needed instead?
<whitequark>
there is no need to do that anywhere in nmigen
<lkcl>
if you can be more specific about what's needed, i can help find it
<whitequark>
i already get filenames from stacktraces just fine
<lkcl>
this stuff is pretty obscure
<lkcl>
ok, so what's needed?
<whitequark>
it's probably fine as-is if there is an option to remove src attrs from verilog
* lkcl
scrolls back a bit
<lkcl>
ok - then i won't worry about it. ping me if ever it turns out to be necessary
<sb0>
key2: is the FPGA actually working properly?
<sb0>
at this price it could be chips that failed tests and got officially discarded...
<lkcl>
sb0: aliexpress hold money in escrow, they don't give it out to the seller for at least a month
<sb0>
in the best case, it's could be chips that someone bought in large quantity for some project and got a big discount for, then some of them got diverted
<lkcl>
so if you register a complaint, they definitely don't get the money.
<sb0>
lkcl: subtle failures inside the FPGA may be hard to detect.
<lkcl>
basically, you have a month in which to test the board comprehensively
<lkcl>
sb0: ack
<lkcl>
it may just be "china pricing". that's extremely common, it's just not published
<lkcl>
freescale have COMPLETELY DIFFERENT pricing structures for the iMX6 than for the rest of the world
<sb0>
"don't worry I wrote 9.9USD on the packing box" :))
<lkcl>
and they only answer enquiries by word-of-mouth, from people *in* china.
<lkcl>
lol
<lkcl>
that's pretty normal, too :)
<sb0>
I wish it were
<sb0>
when I was living in europe I was wasting a lot of time on customs crap and that pissed me off royally
<whitequark>
you lived in *germany*
<key2>
sb: it does wirk
<key2>
work
<_whitenotifier-9>
[nmigen] whitequark created branch back.verilog_strip_src - https://git.io/fhUU5
<_whitenotifier-9>
[m-labs/nmigen] whitequark pushed 1 commit to back.verilog_strip_src [+0/-0/±1] https://git.io/fj3GI
<_whitenotifier-9>
[m-labs/nmigen] whitequark 9b26c31 - back.verilog: allow stripping the src attribute, for cleaner output.