sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
<ZirconiumX> What structure is RTLIL? A DAG?
<lkcl> RTLIL is just an HDL. one that's designed to be machine-readable
<vup> you can check out how it looks using `attacks.py generate -t il`
<lkcl> nobody sane would actually write programs in RTLIL by hand
<ZirconiumX> I'm not trying to write RTLIL by hand
<ZirconiumX> I'm trying to understand how you generate it
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<whitequark> ZirconiumX: nmigen should not permit combinatorial loops, ideally
<whitequark> it can be hard to detect them though
<ZirconiumX> That seems reasonable.
<whitequark> as for shadowing, nmigen signals are emphatically not variables
<whitequark> if you want to use variables, you can use variables
<whitequark> signal = signal << 1
<whitequark> signal = signal * 2
<whitequark> and so on
<ZirconiumX> I thought that was forbidden, or was that a Migen thing?
<whitequark> nope, that's plain old python code that i couldn't be able to forbid even if i wanted to
<whitequark> well, there's just one thing, it's not really correct to call that a "signal" because it is an nmigen "value"
<whitequark> (a signal is a value but not every value is a signal)
<whitequark> other than that it's fine though
<ZirconiumX> That makes sense. Regarding loop hunting, I wouldn't try too hard for it, just try to catch obvious mistakes like this one, I think.
<ZirconiumX> It's my fault for not knowing the semantics of Verilog, I suppose.
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<whitequark> nMigen does not presume that you know anything about Verilog
<whitequark> there's no verilog involved
<whitequark> (unless you specifically request it
<whitequark> ideally, yosys would reliably detect combinatorial loops. it can detect most of them, really
<whitequark> actually hang on
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<whitequark> yeah ho
<whitequark> *no
<whitequark> yosys can't do this in presence of processes
<travis-ci> jhwgh1968/smoltcp#6 (rxtoken_mut - 91be06f : jhwgh1968): The build failed.
<travis-ci> Change view : https://github.com/jhwgh1968/smoltcp/compare/e2fcd0241423^...91be06f302ca
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<travis-ci> jhwgh1968/smoltcp#7 (master - f56666a : Astro): The build passed.
<travis-ci> jhwgh1968/smoltcp#8 (rxtoken_mut - 9c82758 : jhwgh1968): The build has errored.
<travis-ci> jhwgh1968/smoltcp#9 (rxtoken_mut - 234f316 : jhwgh1968): The build is still failing.
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<whitequark> ok, let me fix #30 at last
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<sb0> whitequark: besides homu you have nothing running on lab.m-labs.hk, right?
<whitequark> correct
<whitequark> well, maybe there is something i do not remember. but then it is not important
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<sb0> of course, debian can't shut down properly...
<sb0> whitequark: okay it's running on nixbld now, seems ok with ipv4, v6 should work after dns propagation
<whitequark> ok
<sb0> I also created you an account and added your ssh key
<whitequark> ok, i can login
<sb0> rjo: you have a tmux session running as the gitea account. did you something unusual and/or there is some kind of bug?
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<rjo> sb0: that would surprise me. never touched gitea.
<rjo> sb0: to use your preferred way of expressing it: looks like some nix shit again. typical.
<rjo> same uid, as do astro and matterbridge
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<sb0> well the thing is, there is no "again" since nixos bugs are actually quite rare
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<rjo> bullshit. you even reference nix bugs in the artiq manual.
<sb0> there is one. with that uid thing (assuming this is indeed a nix bug) that makes two
<sb0> considering all the other (often complex) things that work correctly, bugs are indeed rare
<rjo> from what i can tell, considering the time you and others spent on nix so far already conda has been an acual time saver.
<rjo> complexity and failure to get things working right is the thing that people complain about re nix.
<sb0> it doesn't scale and it's not future proof. the new infra does many things that are not possible with conda.
<sb0> plus many annoying things like removing packages manually from anaconda.org are no longer an issue
<sb0> as it turns out, this uid problem is essentially user error
<sb0> well, there is a small nixpkgs bug since it should have caught that problem but did not
<sb0> rjo: can you log out so I can fix it cleanly?
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<mtrbot-ml> [mattermost] <sb10q> @astro I just connected a ZC706 to nixbld
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<jfng1> sb0: yes, minerva should work with caches disabled
<jfng1> have you found issues with it ?
<jfng1> currently, #30 makes ports name vary when minerva is instantiated with or without caches
<sb0> jfng1: I was mostly confused because of #30
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<mtrbot-ml> [mattermost] <astro> sb10q: \o/
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<mtrbot-ml> [mattermost] <sb10q> @astro as for cheaper alternatives to zc706, the Cora Z7-10 might be ok (dual core ARM) but the Cora Z7-07S (single core) definitely is not
<mtrbot-ml> [mattermost] <sb10q> you'd get a XC7Z010, whereas the ZC706 has a XC7Z045
<mtrbot-ml> [mattermost] <sb10q> some of the main differences are, lower area, slighyly slower ARM core, slightly slower fabric (artix-7 vs. kintex-7)
<mtrbot-ml> [mattermost] <sb10q> no transceivers
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<mtrbot-ml> [mattermost] <astro> thanks. the difference is just €110 vs €120 and it'll be my very first fpga.
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