sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<sb0> bradbqc: I suspect that's due to the missing network interface inside the nix sandbox, which makes the flexlm garbage unable to get your MAC address and check that the license file belongs to you
<sb0> bradbqc: you can give this piece of junk any kind of network interface (e.g. tun/tap) with whatever MAC address you want, it's usually happy with it
<mtrbot-ml_> [mattermost] <sb10q> @astro @hartytp I will send the thermostat back today
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<harryho> whitequark: Hi, will oMigen's `timeline` method remain in nMigen? Thanks
<harryho> * `timeline` in migen.genlib.misc
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<Dar1us> well that's a trap for young players.. I put an exit in my vivado pre-synthesis script and it just.. bails out of synthesis altogether since it apparently sources the file..
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<whitequark> harryho: probably not, having random collections of functionality in packages called like "misc" tends to indicate a flaw somewhere else
<whitequark> are you using it for something?
<harryho> whitequark: thanks. I'm adopting misoc/interconnect/wishbone2csr on nmigen-soc. That misoc module uses `timeline` that implements the read/write cycles in Wishbone (b3)
<whitequark> harryho: ok, I see, I'd need to take a look at it
<whitequark> btw, are you working on SoC specifically, or are there other nMigen tasks you'd be willing to look at? I could use some help with #231 and #112
<whitequark> and in particular releasing nmigen 0.1 would let me give more attention to nmigen-soc
<harryho> whitequark: I'll need to implement UART with CSR soon. I'll need to ask @sb10q for approval to work with nMigen.
<harryho> *work with you on nMigen
<whitequark> the reason I am saying this is that your CSR work needs review and a few iterations, but right now I'm busy getting nmigen 0.1 out the door. so that seems more optimal.
<_whitenotifier> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JecMQ
<_whitenotifier> [m-labs/nmigen-boards] whitequark 7db1191 - de0: fix typo.
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<_whitenotifier> [nmigen] whitequark commented on issue #216: Memory port transparency model is flawed - https://git.io/JecDn
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JecDz
<_whitenotifier> [m-labs/nmigen] whitequark de34728 - hdl.ast: prohibit signed divisors.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JecDr
<_whitenotifier> [m-labs/nmigen] whitequark 36a7f41 - back.rtlil: avoid unsoundness for division by zero.
<_whitenotifier> [nmigen] whitequark closed issue #238: Division and modulo are incorrect and unsound - https://git.io/JeZMt
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/593417546?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 82.34% (+0.03%) compared to 751ae33 - https://codecov.io/gh/m-labs/nmigen/commit/de34728bf8740df4169c06ff562716e5c8699f40
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.31%) - https://codecov.io/gh/m-labs/nmigen/commit/de34728bf8740df4169c06ff562716e5c8699f40
<_whitenotifier> [nmigen] Failure. The Travis CI build failed - https://travis-ci.org/m-labs/nmigen/builds/593419447?utm_source=github_status&utm_medium=notification
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JecDp
<_whitenotifier> [m-labs/nmigen] whitequark 964c674 - back.rtlil: avoid unsoundness for division by zero.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/593427230?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 82.54% (+0.19%) compared to de34728 - https://codecov.io/gh/m-labs/nmigen/commit/964c67453fc84b16cb721829a9f717308d0b1a5f
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.34%) - https://codecov.io/gh/m-labs/nmigen/commit/964c67453fc84b16cb721829a9f717308d0b1a5f
<_whitenotifier> [nmigen] Success. 82.35% (+0.01%) compared to de34728 - https://codecov.io/gh/m-labs/nmigen/commit/964c67453fc84b16cb721829a9f717308d0b1a5f
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/593427230?utm_source=github_status&utm_medium=notification
<harryho> whitequark: I'm waiting for @sb10q's advice. But I've got another question: when I try `dir(e.elaborate())` where `e` is an `Elaboratable` in python, it prints stuff as shown in this image: https://i.imgur.com/D7hUpHN.png
<harryho> Seems like the method `_get_attribute()` is missing, but it should be a member function in `Module` class, right?
<harryho> * `_get_submodule()`
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<mtrbot-ml_> [mattermost] <sb10q> artiq on sayma v2: https://hastebin.com/zetuwayuro.rb
<mtrbot-ml_> [mattermost] <sb10q> (first boot)
<mtrbot-ml_> [mattermost] <sb10q> a few problems so far but it's going smoother than v1
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<adamgreig> has anyone got an example of using nmigen with verilator? is there much to it beyond dumping my module as verilog and feeding it in?
<whitequark> nope, just that
<adamgreig> cool, i'll give it a go. hopefully automate it within my existing pytest stuff that currently uses pysim
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<_whitenotifier> [smoltcp] rubdos opened pull request #308: Ethernet feature gate - https://git.io/JecQR
<_whitenotifier> [smoltcp] Success. The Travis CI build passed - https://travis-ci.org/m-labs/smoltcp/builds/593516494?utm_source=github_status&utm_medium=notification
<_whitenotifier> [smoltcp] rubdos synchronize pull request #308: Ethernet feature gate - https://git.io/JecQR
<_whitenotifier> [smoltcp] Success. The Travis CI build passed - https://travis-ci.org/m-labs/smoltcp/builds/593530027?utm_source=github_status&utm_medium=notification
<_whitenotifier> [smoltcp] rubdos commented on pull request #308: Ethernet feature gate - https://git.io/Jec70
<mtrbot-ml_> [mattermost] <sb10q> okay DRTIO is working on sayma v2. guess we can use it to prototype wrpll
<mtrbot-ml_> [mattermost] <sb10q> on the other hand the RTM FPGA looks completely fucked
<mtrbot-ml_> [mattermost] <hartytp> whoo!
<mtrbot-ml_> [mattermost] <hartytp> that's reassuring
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<ZirconiumX> adamgreig: I think you could automate it by hacking nmigen.build into submission
<whitequark> i don't think nmigen.build is relevant here
<whitequark> you could of course use back.verilog and its generated name map to correlate Signals with verilog hierarchical names
<mtrbot-ml_> [mattermost] <sb10q> @rjo do you already know the command to check the DONE status of a FPGA with openocd?
<mtrbot-ml_> [mattermost] <sb10q> other than being on the jtag chain and having a xadc readout the RTM FPGA seems completely dead
<_whitenotifier> [smoltcp] whitequark commented on pull request #308: Ethernet feature gate - https://git.io/Jecdd
<_whitenotifier> [smoltcp] m-labs-homu commented on pull request #308: Ethernet feature gate - https://git.io/JecdF
<_whitenotifier> [m-labs/smoltcp] m-labs-homu pushed 2 commits to auto [+0/-0/±10] https://git.io/Jecdb
<_whitenotifier> [m-labs/smoltcp] rubdos 14bad97 - Add ethernet feature-gate as default.
<_whitenotifier> [smoltcp] m-labs-homu commented on pull request #308: Ethernet feature gate - https://git.io/JecdN
<_whitenotifier> [smoltcp] Success. The Travis CI build passed - https://travis-ci.org/m-labs/smoltcp/builds/593584410?utm_source=github_status&utm_medium=notification
<_whitenotifier> [smoltcp] m-labs-homu commented on pull request #308: Ethernet feature gate - https://git.io/JecFn
<_whitenotifier> [m-labs/smoltcp] m-labs-homu pushed 1 commit to master [+0/-0/±9] https://git.io/JecFc
<_whitenotifier> [smoltcp] m-labs-homu closed pull request #308: Ethernet feature gate - https://git.io/JecQR
<mtrbot-ml_> [mattermost] <hartytp> @sb10q didn't creotech check that before shipping?
<mtrbot-ml_> [mattermost] <hartytp> I thought the idea was that no one touched these boards before basic testing to avoid wasting huge amounts of time
<mtrbot-ml_> [mattermost] <hartytp> The old boards did far too much international travel
<mtrbot-ml_> [mattermost] <sb10q> not sure, they haven't replied yet
<mtrbot-ml_> [mattermost] <hartytp> :(
<_whitenotifier> [smoltcp] Success. The Travis CI build passed - https://travis-ci.org/m-labs/smoltcp/builds/593593222?utm_source=github_status&utm_medium=notification
<mtrbot-ml_> [mattermost] <sb10q> Also I've been pushing them to ship bc 1. It's taking forever 2. We need to test wrpll
<mtrbot-ml_> [mattermost] <sb10q> 2. seems achievable at least, I haven't found any problem on the AMC so far
<mtrbot-ml_> [mattermost] <sb10q> Both DDR banks are working with artiq, flash works, drtio works, power supply looks stable in the crate, and haven't seen any funny crashes
<mtrbot-ml_> [mattermost] <sb10q> That's already a big plus compared to v1
<mtrbot-ml_> [mattermost] <hartytp> wow, that's actually pretty positive :)
<mtrbot-ml_> [mattermost] <hartytp> I think project managing Booster has given me a nervous tick where I add a lot of smiley faces at the end of posts
<mtrbot-ml_> [mattermost] <hartytp> "fucking sort it out because this is completely unacceptable" sounds too harsh
<mtrbot-ml_> [mattermost] <hartytp> ""fucking sort it out because this is completely unacceptable :)" on the other hand seems fine
<_whitenotifier> [smoltcp] MabezDev opened pull request #309: Revert to prevous ordering of TCP options - https://git.io/JecbC
<_whitenotifier> [smoltcp] MabezDev edited pull request #309: Revert to prevous ordering of TCP options - https://git.io/JecbC
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<_whitenotifier> [smoltcp] whitequark commented on pull request #309: Revert to prevous ordering of TCP options - https://git.io/JecbK
<rjo> sb10q: i think xilinx_get_stat does that
<rjo> IIRC DONE is a bit in the STAT register
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<bradbqc> @sb10q: how would I go about exposing an interface to the sandbox? And do I have to create a dummy tun/tap interface or can I just give it the real one (while still being able to use the real one outside of the sandbox)?
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