02:59 <harryho> whitequark: Hi, referring to this issue (https://github.com/m-labs/nmigen/issues/11), there's no way to simulate combinational logic in nmigen v0.1rc1, right?

03:01 <mtrbot-ml> [mattermost] <sb10q> "simulate" how?

03:08 <harryho> umm, for example, `reg1.eq(reg2[:1])` is a comb statement, and I want to know if reg1 gives the expected value when I assign different values in reg2.

03:08 <harryho> this is an extremely simplified example.

03:09 <mtrbot-ml> [mattermost] <sb10q> you can work around it by changing the input synchronously in the simulation generatoe

03:09 <mtrbot-ml> [mattermost] <sb10q> you can work around it by changing the input synchronously in the simulation generator

03:10 <mtrbot-ml> [mattermost] <sb10q> the only thing that isn't supported is asynchronous simulation generators; comb statements work

10:57 <mtrbot-ml> [mattermost] <harryho> @sb10q, whitequark: I pushed some code for the CSR DSL this afternoon on my fork, please take a look. A major change was that I now make `CSRRegister` an Elaboratable that has a `CSRElement`, while allowing the user to add CSR fields by referring to the CSRRegister object. I did it by adding a context manager, and you can see the usage in my `test_csr_dsl` code.

10:58 <mtrbot-ml> [mattermost] <harryho> The documentation still needs improvement tho. Sorry about that.

10:59 <whitequark> I'll take a look soon, probably tomorrow and over the weekend

10:59 <mtrbot-ml> [mattermost] <harryho> Sure thing, thanks for all the comments!!

11:05 <mtrbot-ml> [mattermost] <sb10q> https://repairfaq.org/sam/brochures/ls2br1.htm "Design Features: Headphones: ... The headphones supplied with each Model 220 form an important design feature, for they enable the operator to listen in on the output of the servo control system and thus evaluate the problem of retroreflection and back-scattering"

11:05 <whitequark> reminds me of how I debugged USB transfers with coil whine once

11:23 <Dar1us> got to hook up that pattern matching wetware somehow..

14:48 <adamgreig> does anyone have any small examples of an (n)migen spi slave? just want to get an idea of what a good architecture looks like for such a thing

14:49 <adamgreig> what to do about the cdc mostly I guess, I just want to expose a 32 bit word that gets written and another that is read out on each transaction

14:55 <whitequark> zipcpu has an example of the architecture

14:56 <adamgreig> i found rawslave.v, thanks for the pointer

16:53 <rjo> adamgreig: https://github.com/m-labs/pdq/blob/master/pdq/gateware/spi.py and I have another one (for Sinara Banker and Mirny) that doesn't need any additional clock (purely clocked with clk and cs) will hopefully be release soon.

16:53 <adamgreig> Ah cool, thanks rjo

16:55 <rjo> https://github.com/m-labs/pdq/blob/spi2/pdq/gateware/spi.py for a slightly newer version

18:22 <_whitenotifier> [nmigen] Fatsie opened issue #258: Bikeshed: Packaging existing RTL code with nmigen wrapper - https://git.io/Je0MB

18:30 <_whitenotifier> [nmigen] whitequark commented on issue #258: Bikeshed: Packaging existing RTL code with nmigen wrapper - https://git.io/Je0Mr

18:35 <_whitenotifier> [nmigen] whitequark commented on issue #258: Bikeshed: Packaging existing RTL code with nmigen wrapper - https://git.io/Je0My