01:16 <_whitenotifier> [nmigen] RobertBaruch commented on issue #256: Consider adding a --platform (or -p) option to generate - https://git.io/JeRvl

01:41 <mtrbot-ml> [mattermost] <sb10q> @astro so in your opinion, the zynq trash-hardware-corner-cases make it impossible in practice to use Ethernet unless the SDRAM is also used?

01:42 <mtrbot-ml> [mattermost] <sb10q> this makes it a bit annoying for network-enabled bootloaders...

01:42 <_whitenotifier> [nmigen] whitequark commented on issue #256: Consider adding a --platform (or -p) option to generate - https://git.io/JeRvo

01:42 <whitequark> wait, what?

01:42 <whitequark> you can't use ethernet without sdram?

01:42 <whitequark> that sounds nuts

01:43 <whitequark> does it not have its own buffers?

01:44 <mtrbot-ml> [mattermost] <sb10q> Not sure if there's a mode that would work without DMA?

01:49 <whitequark> ah

01:53 <mtrbot-ml> [mattermost] <sb10q> according to the doc there isn't, the packets go straight into the DMA engine, and then there are typical intellectual-poverty-vendor decisions that make it not work correctly with on-chip memory

01:54 <mtrbot-ml> [mattermost] <sb10q> so, network bootloaders would have to run from the SDRAM

01:59 <mtrbot-ml> [mattermost] <sb10q> or the bootloader could deploy a less shitty Ethernet MAC in the PL, but that also sounds complicated...

02:09 <mtrbot-ml> [mattermost] <sb10q> the suggested startup sequence for zynq has no fewer than three stages of bootloaders (BootROM, FSBL, U-Boot)

08:23 <ZirconiumX> If you declare a signed signal, does it get sign-extended if you add it to a wider signal?

08:36 <whitequark> yes

08:36 <whitequark> that's kind of the point of signed signals

08:37 <whitequark> well, half of it? the other half, changing the behavior of most arithmetic operations

08:52 <mtrbot-ml> [mattermost] <harryho> whitequark, sb10q: Sorry I didn't catch up with the discussion about CSR until today. Here are some questions I have:

08:52 <mtrbot-ml> [mattermost] <harryho>

08:52 <mtrbot-ml> [mattermost] <harryho> 1. Could you clarify what you meant by naming the CSR busses internally? Did you mean the interface signals (re, we, etc)?

08:52 <mtrbot-ml> [mattermost] <harryho>

08:52 <mtrbot-ml> [mattermost] <harryho> 1. If we remove the bus-dependent address (e.g. Wishbone address) from the list of `CSRBank` attributes, wouldn't it be impossible to implement the logic to check whether the bus is accessing the right CSR register? I think instead of requiring setting the address at `CSRBank`'s init, we can let an external class to access to such address attribute when finalising the address mapping.

08:52 <mtrbot-ml> [mattermost] <harryho>

08:52 <mtrbot-ml> [mattermost] <harryho> 2. When you talked about separating CSR bus logic from CSR register logic, do you mean the logic that detects r/w strobes should be separated from the logic that determines which actual CSR fields can be written (i.e. fields that are not read only)? I suppose, the former be in CSR bus and the latter be in CSR DSL, maybe?

08:52 <mtrbot-ml> [mattermost] <harryho>

08:52 <mtrbot-ml> [mattermost] <harryho> 3. Are there any urgent changes needed for the Wishbone Python module?

08:52 <mtrbot-ml> [mattermost] <harryho>

08:52 <mtrbot-ml> [mattermost] <harryho> 4. After we fix the CSR classes, WB interconnect and WB-to-CSR bridge, I'd like to propose a Python module that adopts some part of `misoc.integration.soc_core`: a class that allows init-ing with a base CPU address for CSR banks, makes a WB-to-CSR bridge, interconnects the bridge with the CSR busses in the banks (array of banks?), and generates the CPU address mapping for the fir <message clipped>

08:55 <whitequark> harryho: your last message got clipped after "generates the CPU address mapping"

08:56 <mtrbot-ml> [mattermost] <harryho> ... for the firmware later on (e.g. through a SVD generator and SVD-to-Rust tool).

08:57 <whitequark> CSR signal naming: yes

08:58 <whitequark> two questions re CSR bus logic: I'll hopefully push some code today that answers it

08:58 <whitequark> Wishbone: the layout should at least not be fixed at 32 bits

08:58 <whitequark> the Wishbone spec allows 8, 16, 32 and 64 bit datapath

09:01 <whitequark> soc_core: maybe, but it is usually best to avoid such utility classes by making other components fit together more closely

09:02 <whitequark> if the amount of code required to integrate WB/CSR/registers is 2 or 3 lines, then obviously there is no need for a class, since it is trivial to instantiate that for any sort of SoC

09:43 <_whitenotifier> [nmigen-boards] ZirconiumX synchronize pull request #33: Add DE10-Nano-based MiSTer - https://git.io/JelOb

09:43 <_whitenotifier> [nmigen-boards] ZirconiumX commented on pull request #33: Add DE10-Nano-based MiSTer - https://git.io/JeRq2

10:28 <ZirconiumX> So, I updated my nMigen and found Signal((3, True)) is deprecated for Signal(signed(3)), except that the latter gives a NameError that signed is not defined

10:28 <ZirconiumX> I'm probably missing something

10:31 <whitequark> how are you importing Signal ?

10:31 <ZirconiumX> Okay, yeah, I needed to import it from nmigen

10:31 <ZirconiumX> from nmigen import Signal

10:33 <ZirconiumX> I have a snippet of "from nmigen import Elaboratable, Module, Signal; from nmigen.back import pysim, verilog" because I need to do it so much

11:32 <whitequark> ZirconiumX: `from nmigen import *`

11:32 <_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JeRYS

11:32 <_whitenotifier> [m-labs/nmigen] whitequark 61e6267 - Explicitly restrict prelude imports.

11:36 <ZirconiumX> Right, okay

11:50 <_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/600690929?utm_source=github_status&utm_medium=notification

11:50 <_whitenotifier> [nmigen] Success. 82.37% (+0.1%) compared to 9fba5cc - https://codecov.io/gh/m-labs/nmigen/commit/61e6267dafa4e4cde711c91509bd825e6e6839a6

11:50 <_whitenotifier> [nmigen] Success. Coverage not affected when comparing 9fba5cc...61e6267 - https://codecov.io/gh/m-labs/nmigen/commit/61e6267dafa4e4cde711c91509bd825e6e6839a6

11:51 <_whitenotifier> [nmigen] Success. 82.26% remains the same compared to 9fba5cc - https://codecov.io/gh/m-labs/nmigen/commit/61e6267dafa4e4cde711c91509bd825e6e6839a6

11:51 <_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/600690929?utm_source=github_status&utm_medium=notification

15:07 <_whitenotifier> [m-labs/nmigen-soc] whitequark pushed 1 commit to master [+4/-0/±1] https://git.io/JeRZw

15:07 <_whitenotifier> [m-labs/nmigen-soc] whitequark dc918fc - csr.bus: add CSRElement and CSRMultiplexer.

16:23 <mtrbot-ml> [mattermost] <astro> @sb10q I honestly don't know yet

16:34 <_whitenotifier> [nmigen-soc] jordens commented on commit dc918fc20b667c24bd91cf2b9b2e6ef6c69e12e0 - https://git.io/JeRCf

16:45 <_whitenotifier> [nmigen-soc] whitequark commented on commit dc918fc20b667c24bd91cf2b9b2e6ef6c69e12e0 - https://git.io/JeRCl

16:51 <_whitenotifier> [nmigen-soc] whitequark commented on commit dc918fc20b667c24bd91cf2b9b2e6ef6c69e12e0 - https://git.io/JeRCu

17:00 <_whitenotifier> [nmigen-soc] jordens commented on commit dc918fc20b667c24bd91cf2b9b2e6ef6c69e12e0 - https://git.io/JeRCX

17:13 <mtrbot-ml> [mattermost] <astro> the zc706 has been disconnected from nixbld. I'll continue with my cora z7-10 for now...

17:27 <_whitenotifier> [nmigen-soc] whitequark commented on commit dc918fc20b667c24bd91cf2b9b2e6ef6c69e12e0 - https://git.io/JeRW3

17:28 <bradbqc> sb10q: can you provide any more hints? I've tried to do what you said but can't seem to figure it out. I created a security wrapper for pkgs.iproute.ip with added net_admin capability and then added /run/wrappers to sandboxPaths but I keep getting a "file does not exist" when I try to execute it from within vivado.nix

18:15 <_whitenotifier> [nmigen-soc] jordens commented on commit dc918fc20b667c24bd91cf2b9b2e6ef6c69e12e0 - https://git.io/JeRlw

19:05 <bradbqc> Even if I disable sandboxing I get "cannot raise the capability into the Ambient set" (which I don't get when running the wrapped ip executable in a normal shell)

22:12 <_whitenotifier> [nmigen] RobertBaruch commented on issue #256: Consider adding a --platform (or -p) option to generate - https://git.io/JeREB