<mtrbot-ml_>
[mattermost] <sb10q> @hartytp @astro OK to send the thermostat board back to Oxford?
<_whitenotifier>
[nmigen-boards] whitequark commented on issue #21: Refactor awkward use of attributes - https://git.io/Jecco
<_whitenotifier>
[nmigen-boards] whitequark closed issue #21: Refactor awkward use of attributes - https://git.io/fjizT
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<ZirconiumX>
whitequark: DE0 without the CV is Cyclone III based. It's not even supported by Quartus anymore.
<ZirconiumX>
But just to check, could you read the part number off the chip?
<whitequark>
well i just made a board file for it then
<whitequark>
ep3cf16f484c6n
<ZirconiumX>
Yep, EP3 is Cyclone III
<whitequark>
;w;
<whitequark>
ok well i actually downloaded quartus 13.1
<ZirconiumX>
With a whopping 15k LEs
<whitequark>
how do i make a .sof file btw?
<whitequark>
or whatever it is quartus_pgm will eat
<ZirconiumX>
To make a .sof you remove the "GENERATE_RBF_FILE" line in the .qsf
<whitequark>
uh. can it make both?
<ZirconiumX>
... I'd have to check
<ZirconiumX>
I'm running on slight sleep deprivation
<ZirconiumX>
whitequark: Yeah it builds a .sof as well as a .rbf with GENERATE_RBF_FILE on
<whitequark>
ah cool
<ZirconiumX>
I'm curious how well the board will perform compared to e.g. Glasgow, because it's comparatively pretty old, but it was a good chip for its time
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<ZirconiumX>
whitequark: also there's an annoying minor typo in my branch that you squashed; line 370 has an else that is somehow one space less than the if it matches
<whitequark>
yeah, i fixed it locally
<whitequark>
by Glasgow you mean HX8K?
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<ZirconiumX>
Yep
<ZirconiumX>
iCE40 in general I guess
<whitequark>
ZirconiumX: wheeeeee it's blinking
<ZirconiumX>
Woo
<ZirconiumX>
But the blinking was essentially the stuff you did
<whitequark>
i mean, it's the first time i ever programmed an altera device
<whitequark>
i didn't actually use them before
<ZirconiumX>
True, I suppose
<ZirconiumX>
Did you use quartus_pgm for it?
<whitequark>
yeah
<whitequark>
i ran jtagd --user-start after making the appropriate udev rules
* ZirconiumX
grumbles about it not working for their DE-10
<whitequark>
how are you running it exactly
<whitequark>
?
<ZirconiumX>
ZirconiumX: I'm running on slight sleep deprivation
<ZirconiumX>
Uuuh
<ZirconiumX>
I don't even have my board with me at present and it's not in my .bash_history
<ZirconiumX>
The GUI programmer didn't even work, let alone the CLI one
<whitequark>
i've never used quartus' gui
<_whitenotifier>
[m-labs/nmigen-boards] whitequark pushed 3 commits to master [+8/-10/±16] https://git.io/JeclT
<_whitenotifier>
[m-labs/nmigen-boards] whitequark b033d53 - Factor out "sd_card_{1bit,4bit,spi}" resources.
<_whitenotifier>
[m-labs/nmigen-boards] whitequark 50acf4a - [breaking-change] Fix polarity of "dm" signal in "memory" resource.
<_whitenotifier>
[m-labs/nmigen-boards] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/Jeclk
<_whitenotifier>
[m-labs/nmigen-boards] whitequark 07156e6 - Factor out "sdram" resource.
<_whitenotifier>
[m-labs/nmigen-boards] whitequark b50e52c - Factor out "nor_flash" resource.
<ZirconiumX>
The windows version is called quartus_pgmw
<ZirconiumX>
For its GUI version
<whitequark>
i have _pgmw on windows too
<whitequark>
er
<whitequark>
onlinux too
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<ZirconiumX>
whitequark: if you're going to add Quartus support, could I suggest having some way of dumping ROM/RAM init files externally and emitting a $readmemh or whatever the equivalent RTLIL is?
<ZirconiumX>
As we found out the hard way, Quartus doesn't like long `initial` type statements
<whitequark>
ZirconiumX: that's dependent on yosys supporting it
<whitequark>
there's no RTLIL for "$readmemh" and there can't really be
<whitequark>
however, yosys' write_verilog can be taught to extract memory contents
<ZirconiumX>
I think that would work too.
<ZirconiumX>
Quartus has its own weird .mif format, but I think supports boring .hex too.
<_whitenotifier>
[m-labs/nmigen-boards] whitequark pushed 2 commits to master [+1/-0/±1] https://git.io/Jec8a
<whitequark>
now i have 2x disk space occupied by quartus, too
<ZirconiumX>
To be fair Terasic have the worst naming scheme I've ever seen
<whitequark>
yeah word.
<whitequark>
i feel like a surprisingly high amount of decisions in the altera ecosystem are just kind of ... really bad
<whitequark>
even by fpga vendor standards
<whitequark>
makes total sense that intel would buy it :p
<ZirconiumX>
whitequark: It's inherent in the very fibre of Altera's being
<ZirconiumX>
For example: what's the name of the primitive for instantiating a LUT?
<ZirconiumX>
On the Cyclone V, it's arriav_lcell_comb; on the Cyclone IV it's fiftyfivenm_lcell_comb
<ZirconiumX>
A RAM block. On the Cyclone V, it's generic_m10k; on the Cyclone IV, it's cycloneiv_ram_block
<ZirconiumX>
You can't make this shit up
<whitequark>
i'm sorryw hat
<whitequark>
arriav_lcell_comb? on cyclone v?
<ZirconiumX>
Give me a sec, and I'll demonstrate the insanity of this.
<ZirconiumX>
I should point out that this has gotten bad enough that the compiler, whenever it infers RAM, doesn't infer the correct RAM block but instead the altsyncram IP core
<ZirconiumX>
Which then translates into the correct-ish RAM block
<ZirconiumX>
arriav_lcell_comb, but stratixv_ram_block
<ZirconiumX>
whitequark: Your computer may need an exorcism after we're done with this
<whitequark>
oh it's seen much worse, trust me
<ZirconiumX>
Considering this is *you* we're talking about, I don't doubt that
<ZirconiumX>
wq: On a somewhat more serious note, can you port de10_nano to the resources folder that you've added?
<ZirconiumX>
Another question I have: m-labs/nmigen-boards#29 (the DE-10 Nano branch) is blocked on vendor.altera, but DE0 gets merged straight into master despite having the same dependency
<whitequark>
ZirconiumX: i've merged it because it's complete
<whitequark>
de10nano isn't
<ZirconiumX>
Guess I know what I'm working on next then
<whitequark>
you still can't actually use de0 but at least i've tested it
<whitequark>
actually
<whitequark>
if you ported de0cv it'd help me more
<whitequark>
since de0cv is what i'm going to test things on
<whitequark>
once it arrives
<ZirconiumX>
(tm)
<ZirconiumX>
But first: breakfast
<_whitenotifier>
[m-labs/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jec4G
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<_whitenotifier>
[nmigen] whitequark opened issue #244: Reliable installation on Windows - https://git.io/Jec4C
<_whitenotifier>
[nmigen] whitequark commented on issue #242: bitarray dependency is unfortunate - https://git.io/Jec4W
<whitequark>
ZirconiumX: why tf does de0cv have the same clock buffered to 4 different banks?
<ZirconiumX>
whitequark: I have no idea
<ZirconiumX>
Gotta say, the user manual for the DE-0 CV is...lacking
<whitequark>
lol
<ZirconiumX>
Also the manuals continue to piss me off greatly by listing a made-up number of LEs
<ZirconiumX>
The original Cyclone chips were LUT4 + DFF based, and this was a logic element
<ZirconiumX>
Then when they moved to the LUT6 + 4xDFF adaptable logic module architecture, they continued to brand it in LEs by multiplying the number of ALMs by 2.5.
<ZirconiumX>
See for example the chip in the DE-10 Nano which is branded as having 110K LEs, despite actually containing ~42K ALMs
* ZirconiumX
grumbles
<whitequark>
lol
<ZirconiumX>
Yeah I'm slightly salty
<daveshah>
Everyone does this
<daveshah>
Xilinx do it too, although I think their factor is a bit smaller (1.6 ish for xc7, 2 ish for xcup)
<ZirconiumX>
Lies, damned lies and FPGA LUT counts
<mtrbot-ml_>
[mattermost] <sb10q> do serious FPGA programmers even read those LE/"logic cells" ratings?
<daveshah>
They're a reasonable way to compare FPGAs within a family, as a monotonic value for size
<mtrbot-ml_>
[mattermost] <sb10q> okay, but so is the DFF count, which corresponds to something actually present on the chip and not the result of an undocumented equation made up by marketing people
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<mtrbot-ml_>
[mattermost] <astro> @sb10q I think the thermostat can be shipped away now
<whitequark>
since it had basically nothing useful in it
<ZirconiumX>
whitequark: We should probably put the board programming snippet in nmigen.vendor.altera
<ZirconiumX>
Given you got it to work
<whitequark>
ZirconiumX: nop
<whitequark>
not all boards will have usb blaster on it
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<ZirconiumX>
So, one problem with the DE10 is that it's a SoC, and it's a bit difficult to tell which bits go to the FPGA and which to the ARM
<ZirconiumX>
>.>
<whitequark>
yeah, that's why i avoid it
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<bradbqc>
Has anyone had any issues with Xilinx licenses in NixOS? I have a kc705 eval license and I'm able to build a sample project for it through the vivado gui, but when I try to build any gateware for it (through a local hydra installation) it can't find the license. I've tried moving the license file around and setting the XILINXD_LICENSE_FILE variable
<bradbqc>
but nothing has worked so far
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<ZirconiumX>
whitequark: thoughts on having some way to use Verilator as an alternative simulation backend, possibly through (ab)using nmigen.build? pysim is nice, but slow, and I have no idea if the fundamental problem of "it's python" can be resolved.