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_whitenotifier>
[nmigen] RobertBaruch commented on issue #211: Right way to express a bundle of Signals? -
https://git.io/Je3Nk
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whitequark>
ZirconiumX: yeah something like this
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_whitenotifier>
[nmigen] whitequark commented on issue #211: Right way to express a bundle of Signals? -
https://git.io/Je3AQ
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_whitenotifier>
[m-labs/nmigen] whitequark f6f0a7b - lib.fifo: simplify. NFC.
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_whitenotifier>
[nmigen] whitequark opened issue #219: AsyncFIFO[Buffered] initialization is unergonomic -
https://git.io/Je3xb
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_whitenotifier>
[m-labs/nmigen] whitequark a13a21c - hdl.ast: update docs. NFC.
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_whitenotifier>
[m-labs/nmigen] whitequark 2dc6ae4 - lib.fifo: update docs. NFC.
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ZirconiumX>
Well, altiobuf wants you to instantiate it before using it, and I don't much feel like dealing with
*that*
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whitequark>
instantiate what
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ZirconiumX>
It's an IP core
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ZirconiumX>
Error (12006): Node instance "$8" instantiates undefined entity "altiobuf". Ensure that required library paths are speci
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ZirconiumX>
party IP, generate the synthesis files for the IP.
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ZirconiumX>
fied correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-
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whitequark>
isn't this a missing library path
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ZirconiumX>
No, this is "Intel FPGA IP"
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ZirconiumX>
Time for a different approach...
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_whitenotifier>
[m-labs/nmigen] whitequark 07a82ed - build.plat: NMIGEN_<toolchain>_env→NMIGEN_ENV_<toolchain>
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_whitenotifier>
[m-labs/nmigen] whitequark 8050cfa - build.res: simplify clock constraints.
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_whitenotifier>
[m-labs/nmigen] whitequark 3d62dac - vendor.lattice_ice40: add iCECube support.
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_whitenotifier>
[m-labs/nmigen-boards] whitequark cb0c2cd - Fix IO_STANDARD on all iCE40 boards.
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whitequark>
ZirconiumX: is it case-sensitive?
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whitequark>
the doc calls it ALTIOBUF, not altiobuf
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ZirconiumX>
whitequark: It's lower case; I instantiated it manually to check
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ZirconiumX>
I'm going to try a different approach
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ZirconiumX>
They have a lower-level primitive called alt_{in,out,io}buf
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ZirconiumX>
Yes, they have an IP core called altiobuf and a primitive called alt_iobuf
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_whitenotifier>
[nmigen] whitequark opened issue #220: Prune Yosys-internal attributes in emitted Verilog -
https://git.io/JesJm
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_whitenotifier>
[nmigen] ZirconiumX commented on issue #220: Prune Yosys-internal attributes in emitted Verilog -
https://git.io/JesJY
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_whitenotifier>
[nmigen] daveshah1 commented on issue #220: Prune Yosys-internal attributes in emitted Verilog -
https://git.io/JesJs
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_whitenotifier>
[nmigen] whitequark commented on issue #220: Prune Yosys-internal attributes in emitted Verilog -
https://git.io/JesJZ
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_whitenotifier>
[nmigen] whitequark commented on issue #220: Prune Yosys-internal attributes in emitted Verilog -
https://git.io/JesJE
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_whitenotifier>
[nmigen] daveshah1 commented on issue #220: Prune Yosys-internal attributes in emitted Verilog -
https://git.io/JesJu
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ZirconiumX>
whitequark: I have gotten an alt_outbuf based blinky to build and run
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ZirconiumX>
For whatever that's worth
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ZirconiumX>
Is there something I can use to test SDR?
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whitequark>
you'd need to add some logic
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whitequark>
ideally watch it with a scope
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_whitenotifier>
[nmigen] RobertBaruch commented on issue #211: Right way to express a bundle of Signals? -
https://git.io/JesUf
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_whitenotifier>
[nmigen] RobertBaruch closed issue #211: Right way to express a bundle of Signals? -
https://git.io/Je3mW
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_whitenotifier>
[nmigen] ZirconiumX opened pull request #221: vendor.altera: use buffer primitives -
https://git.io/JesUg
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_whitenotifier>
[nmigen] codecov[bot] commented on pull request #221: vendor.altera: use buffer primitives -
https://git.io/JesUV
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_whitenotifier>
[nmigen] ZirconiumX commented on pull request #221: vendor.altera: use buffer primitives -
https://git.io/JesL5
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