sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<_whitenotifier> [nmigen] RobertBaruch synchronize pull request #204: Adds Value.matches - https://git.io/JemSc
<_whitenotifier> [nmigen] RobertBaruch reviewed pull request #204 commit - https://git.io/JeYtO
<_whitenotifier> [nmigen] whitequark reviewed pull request #204 commit - https://git.io/JeYtG
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584393920?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. Absolute coverage decreased by -0.08% but relative coverage increased by +3.85% compared to 8c30147 - https://codecov.io/gh/m-labs/nmigen/compare/8c30147e39ccc19294ab2d62888dc1e70b0672b5...d2d13f414b6afdc701b853794374e2ef335c71a9
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584393920?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] programmerjake commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JeYtR
<_whitenotifier> [nmigen] RobertBaruch synchronize pull request #204: Adds Value.matches - https://git.io/JemSc
<_whitenotifier> [nmigen] RobertBaruch reviewed pull request #204 commit - https://git.io/JeYtV
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584402500?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584402500?utm_source=github_status&utm_medium=notification
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<sb0> rjo: how you load the redpid gateware into redpitaya?
<sb0> whitequark: your diff link in https://github.com/m-labs/nmigen/issues/97#issuecomment-530985343 is broken
<sb0> the fifo diff looks ok
<mtrbot-ml> [mattermost] <sb10q> @astro thermostat is rebooted
<mtrbot-ml> [mattermost] <sb10q> @astro ping re. allocator
<sb0> rjo: and how do you initialize the ADC/DAC? do you rely on other parts of the redpitaya software stack?
<mtrbot-ml> [mattermost] <sb10q> @cjbe your stabilizer commit messed up permissions
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<Dar1us> hi everyone
<Dar1us> I am trying Migen with a Spartan 3 board I have lying around (working through https://github.com/litex-hub/fpga_101/). I adjusted the IOs to match my board and changed the device. It builds but after programming it nothing happens
<Dar1us> oh I ran bitgen by hand to specify -g StartUpClk:JTagClk otherwise djtgcfg complains
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<daveshah> P184 on clk50 doesn't look right
<daveshah> Oh, it's not a bga, never mind
<Dar1us> daveshah: this is old school PQ208 :)
<Dar1us> it's this board
<Dar1us> I have their seven_seg.v demo project working
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<rjo> sb0: just cat it into that special device in /dev forgot the name
<rjo> sb0: iirc the fast adc and dacs don't need initialization. the slow ones are a delta-sigma and the XADC.
<sb0> okay, I'm only interested in the fast ADC
<sb0> nice
<sb0> so, I guess we can strip the existing software quite easily and just use migen-axi + the zc706 rust code
<Dar1us> "zc706 rust code"?
<Dar1us> (if you don't mind my curiosity!)
<sb0> Dar1us: smoltcp and bare metal rust on zynq
<Dar1us> wow, very cool :)
<Dar1us> I haven't got much past blinky LED with rust on STM32
<sb0> I want to use a red pitaya to retrofit a michelson laser wavemeter from 1983 and add fourier transform capabilities
<sb0> the whole thing would cost <$1k instead of ~30k from thorlabs, with similar capabilities
<sb0> FT can show many things about diode laser modes, and unlike SFPIs don't involve unobtainium wavelength-limited mirrors with finicky alignment and FSR issues
<Dar1us> sb0: sounds like a pretty cool hack if you can get it working
<rjo> sb0: you can also borrow from https://github.com/japaric/ultrascale-plus if you are not already aware.
<sb0> the wavemeter has a diagnostics connector with the outputs from the photodiode amps, so that'll be easy to connect
<rjo> sb0: lots of tooling for rust on US+
<sb0> and it's already working with the original fringe counting and PLL electronics, which surprisingly survived, and outputs nice sine waves on the diags connector
<sb0> rjo: thanks
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<ZirconiumX> I have a question about intermediate result precision; if you take "(x * y) >> 4", where x and y are 16-bit values, what precision is the `(x * y)` performed at?
<ZirconiumX> Verilog I think would do it at 16-bit precision and then end up truncating the result
<whitequark> ZirconiumX: at full precision
<whitequark> i.e. `x * y` is wide enough to represent any multiplication result
<ZirconiumX> So, 32-bit precision, then?
<whitequark> yeahyeah
<whitequark> *yeah
<ZirconiumX> Thank you
<ZirconiumX> Back to getting confused with fixed-point math, then
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<mtrbot-ml> [mattermost] <hartytp> @astro what’s the best way of controlling pwm in your code?
<_whitenotifier> [nmigen] whitequark deleted branch lib.fifo-conventions - https://git.io/fhUU5
<_whitenotifier> [m-labs/nmigen] whitequark deleted branch lib.fifo-conventions
<_whitenotifier> [nmigen] whitequark deleted branch pysim-split-funclets - https://git.io/fhUU5
<_whitenotifier> [m-labs/nmigen] whitequark deleted branch pysim-split-funclets
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±4] https://git.io/JeYZr
<_whitenotifier> [m-labs/nmigen] whitequark da4b810 - lib.fifo: adjust properties to have consistent naming.
<_whitenotifier> [m-labs/nmigen] whitequark bdb70ad - lib.fifo: adjust for new CDC primitive conventions.
<_whitenotifier> [nmigen] whitequark closed issue #97: Bikeshed: conventions for CDC primitives - https://git.io/fjgRI
<_whitenotifier> [nmigen] whitequark commented on pull request #40: WIP: Expand and document lib.cdc - https://git.io/JeYZ6
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<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584576644?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 82.79% (+0.01%) compared to b92e967 - https://codecov.io/gh/m-labs/nmigen/commit/bdb70ad45f71b55ce8d02f329b51ee38970a5642
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.78%) - https://codecov.io/gh/m-labs/nmigen/commit/bdb70ad45f71b55ce8d02f329b51ee38970a5642
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<mtrbot-ml> [mattermost] <hartytp> Do you plan to add a tec driver module soon
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±5] https://git.io/JeYnB
<_whitenotifier> [m-labs/nmigen] whitequark b23a979 - hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}.
<_whitenotifier> [nmigen] whitequark commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JeYnR
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584591356?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 82.96% (+0.16%) compared to bdb70ad - https://codecov.io/gh/m-labs/nmigen/commit/b23a9794a4cfc5b246cde2b28bc735a98c2eccdc
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 82.79%) - https://codecov.io/gh/m-labs/nmigen/commit/b23a9794a4cfc5b246cde2b28bc735a98c2eccdc
<_whitenotifier> [nmigen] Success. 82.83% (+0.03%) compared to bdb70ad - https://codecov.io/gh/m-labs/nmigen/commit/b23a9794a4cfc5b246cde2b28bc735a98c2eccdc
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584591356?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] whitequark commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JeYc4
<_whitenotifier> [nmigen] whitequark commented on issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/JeYc0
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±4] https://git.io/JeYCf
<_whitenotifier> [m-labs/nmigen] whitequark 0a00d53 - hdl.ast: add VAlue.xor, mapping to $reduce_xor.
<_whitenotifier> [nmigen] whitequark closed issue #147: Expose primitive AND, OR, NAND, NOR, XOR, XNOR operations under descriptive names - https://git.io/fjXCK
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±4] https://git.io/JeYCT
<_whitenotifier> [m-labs/nmigen] whitequark 32310ae - hdl.ast: add Value.xor, mapping to $reduce_xor.
<_whitenotifier> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/584622664?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/584622664?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584623105?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. 82.75% (-0.08%) compared to b23a979 - https://codecov.io/gh/m-labs/nmigen/commit/32310aecad7cbf45c26e7dbd28bb1676453e0920
<_whitenotifier> [nmigen] Failure. 50% of diff hit (target 82.83%) - https://codecov.io/gh/m-labs/nmigen/commit/32310aecad7cbf45c26e7dbd28bb1676453e0920
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/584623105?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] whitequark closed issue #144: allow multiple processes to run at same simulated time - https://git.io/fjPIX
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<ZirconiumX> Possibly stupid, but what would you use an nMigen Record for?
<ZirconiumX> An MMIO register?
<whitequark> it's like a C struct
<whitequark> except unlike in C you can use bitfields
<mtrbot-ml> [mattermost] <casperc> casperc joined the team.
<whitequark> for example
<ZirconiumX> I'll have a play around with it and see
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<ZirconiumX> wq: Would you recommend control registers be written using a Record, or with a bunch of Signals?
<whitequark> what sort of control registers?
<ZirconiumX> Data inputs come in as register writes for this
<ZirconiumX> Things like input coordinates
<ZirconiumX> Interrupt status
<whitequark> if it's a bunch of signals that are inherently ordered and are sometimes written or read together, use a Record
<whitequark> a Record is basically the same as Cat(f1, f2, f3)
<ZirconiumX> Right, thank you
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<ZirconiumX> Another nMigen thing: how do you share something between nMigen modules? For example, a framebuffer that the pixel pipeline needs to read/write from, and the video circuitry needs to read
<ZirconiumX> Maybe take it as a parameter in __init__, store it in self and then use it in elaborate?
<mtrbot-ml> [mattermost] <hartytp> @astro reading over the code and getting up to speed
<mtrbot-ml> [mattermost] <hartytp> (CH_EN is bit 15)
<emily> I also wonder about large-scale organization questions like ZirconiumX's; in Clash the types tell you how everything plugs together, but in nmigen I'm not sure what you're meant to do.
<_whitenotifier> [nmigen] dlharmon commented on issue #200: nextpnr does not propagate clock constraints across input buffer - https://git.io/JeY45
<_whitenotifier> [nmigen] dlharmon closed issue #200: nextpnr does not propagate clock constraints across input buffer - https://git.io/Jeqwc
<whitequark> emily: it's pretty much all by convention
<whitequark> and oMigen's conventions weren't all that consistent. I'm working on making them more consistent as I go, but a lot of it is certainly subjective
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<mtrbot-ml> [mattermost] <astro> @hartytp bit 15 of 16-bits = byte 0 bit 7 of byte 0 of 2-bytes
<mtrbot-ml> [mattermost] <astro> @hartytp I still have to move PWM setup out of board initialization to make it remote-controllable.
<mtrbot-ml> [mattermost] <astro> @hartytp the pid.rs is still unmodified from ionpak
<mtrbot-ml> [mattermost] <hartytp> Ack
<mtrbot-ml> [mattermost] <hartytp> Thanks!
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<mtrbot-ml> [mattermost] <astro> @sb10q the allocator is needed for the owned_box lang_item, needed for the "logos" parser crate. the compiler started complaining when I had already written some of the parser code and I'd love to sink more time into this... but a usable prototype has higher priority for now.
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