14:05 <Streetwalrus> hi, I was wondering why python was chosen for migen and nmigen

14:07 <Streetwalrus> migen is a really nice approach and I also love python

14:08 <Streetwalrus> but python feels like a weird choice

14:10 <Streetwalrus> it's not very good at anything low level nor at hosting embedded DSLs

14:11 <emily> dunno about migen but for (n)migen/Glasgow I think it comes down to "because nobody would use it if it was in OCaml"

14:11 <emily> I don't think whitequark has much love for Python.

14:11 <Streetwalrus> well that's fair enough but there's plenty of more viable options

14:14 <Streetwalrus> chisel and spinalhdl benefit from a much nicer syntax in scala, though that's also far from perfect

14:18 <Streetwalrus> I still haven't really looked into the Haskell options either because Haskell

14:21 <mtrbot-ml> [mattermost] <sb10q> many people also don't look into scala options because scala

14:22 <Streetwalrus> scala is a neat language

14:23 <Streetwalrus> main gripe is the java runtime dependency

14:32 <whitequark> Streetwalrus: scala, haskell and ocaml are essentially equally obscure if you talk to people who come from Verilog

14:33 <Streetwalrus> good point

14:33 <whitequark> (n)migen isn't really something new and revolutionary; it doesn't try to experiement with radical semantics that requires a large effort for a large payoff. rather, it's a way to express RTL that isn't as boneheaded as Verilog used for that task

14:34 <Streetwalrus> yeah I know how it works

14:34 <whitequark> indeed

14:34 <Streetwalrus> I've only worked with vhdl but it's the same problem

14:34 <whitequark> the main advantage of vhdl in this area is deterministic simulation

14:35 <whitequark> but it doesn't buy that much

14:38 <emily> Streetwalrus: well, as a (former) Haskeller I haven't looked into the Scala options because Scala :p

14:38 <emily> Python is a lowest-common denominator language that we can all happily hate

14:38 <whitequark> it could have been javascript

14:38 <Streetwalrus> oh no

14:46 <Streetwalrus> I guess the hardest part will always be reconciling those who come from a hardware background and those who come from software

14:47 <Streetwalrus> I'm the latter and I can't stand writing vhdl

14:47 <daveshah> The irony being that behavioural VHDL and Verilog are nothing like "hardware"

14:48 <whitequark> ^

14:48 <Streetwalrus> yeah

14:48 <Streetwalrus> the lack of proper metaprogramming is also a huge handicap

14:53 <whitequark> i wouldn't use clash because of the lack of correspondence between the source and the generated code in signal names; i don't even think nmigen is quite good enough on that

14:53 <whitequark> not sure how chisel and spinalhdl fare there

14:54 <Streetwalrus> I haven't really looked into it either

18:32 <davidc__> Streetwalrus: I think python is a good choice for migen/nmigen _because_ it is not a special purpose language. I regularly use migen code as part of a larger python projects (ex: implement gateware to do a small part of a much larger system including firmware and host software)

18:33 <davidc__> Streetwalrus: because its just python; its easy to move data back and forth between components (Ex: register maps, or filter taps, or data for connector pinouts, etc)

18:33 <davidc__> Streetwalrus: Sure, one could do that in another language; but then you're writing your data marshalling code twice

22:37 <key2> how would it be with js ?

22:39 <ZirconiumX> key2: Painful

22:40 <key2> and in Ocaml ?

22:41 <whitequark> there's already hardcaml

22:41 <ZirconiumX> Possibly painful for a different reason, if you're not used to the strong typing of OCaml

22:43 <whitequark> it's so popular, i've never seen anyone use it. the repository doesn't have any commits or issues for years

22:43 <whitequark> i expect that i'd be the only person using it on a regular basis if i chose to use it