<lekernel>
il tourne aussi sur plusieurs cartes xilinx/altera
<vr1>
salut les gars
<wpwrak>
lekernel: i hope i haven't just added a 2 month delay to MM1 progress ;-)
<lekernel>
wpwrak: ?
<wpwrak>
lekernel: see the qi-hw mailing list ;-)
<wpwrak>
lekernel: well, or maybe don't :)
<lekernel>
the robot?
<wpwrak>
yeah
<wpwrak>
looks cool, doesn't it ? and it also looks kinda doable ...
<lekernel>
heard of boston dynamics?
<lekernel>
(big dog etc.)
<wpwrak>
yup
<wpwrak>
kinda scary that device. looks a bit too "alive"
<wpwrak>
what i like about the rotopod is its symmetry - all the six axes are identical. so you don't need to design each axis separately, like in traditional CNC machines.
<lekernel>
!karma test
<CIA-8>
milkymist: Sebastien Bourdeauducq newmac * r99be230 / (10 files in 3 dirs): minimac2: TX working in simulation - http://bit.ly/fcr6dh
<larsc>
mwalle: something is wrong with the scall code generation. http://pastebin.com/3KVHpa7t there is only an scall instruction at 40017c58
<larsc>
finally:
<larsc>
VFS: Mounted root (ext2 filesystem) readonly on device 1:0.
<larsc>
HELLO WORLD
<larsc>
Kernel panic - not syncing: Attempted to kill init!
<mwalle>
larsc:
<mwalle>
is scall broken?
<larsc>
mwalle: i reverted d53066a5578945748dd7d8099c96de13f9a69211 and now it works again
<mwalle>
larsc: could you please paste the code arount 40017c58?
<larsc>
well, there is one scall plus a few mv
<mwalle>
do you know what happens?
<larsc>
not really
<larsc>
for some reasons scall exceptions are also created for the lines following the real scall
<mwalle>
mh so why doesn't this happen with test_scall.S?!
<larsc>
test_scall.S?
<mwalle>
qemu/tests/lm32/
<mwalle>
make check
<larsc>
hm
<mwalle>
larsc: could you upload your kernel and initrd?
<mwalle>
mh i think i dont need it
<mwalle>
happens for me too
<mwalle>
mh ok, works again ;)
<mwalle>
larsc: i just uploaded the fix
<larsc>
nice
<larsc>
:)
<mwalle>
narf, commit contains opengl 'fix'..
<mwalle>
larsc: i guess you already pulled it :)
<larsc>
fell free to rebase
<mwalle>
done
<TS-Labs>
hello!
<TS-Labs>
i have a question about Navre AVR clone
<mwalle>
hi
<TS-Labs>
as it is said in description, the classic avr instruction set is supported. but when reading the sources I see that the MUL's aren't implemented
<mwalle>
i guess it isnt needed by us. so it may not be implemented
<mwalle>
esp. since multipliers needs lots of ressourecs
<TS-Labs>
yeah, ok )
<mwalle>
or its done in software
<TS-Labs>
in fact, 8bits by 8 multiplier ate ~110 LE's on Acex I Altera
<mwalle>
pipelined?
<TS-Labs>
no, just * in verilog )
<TS-Labs>
combinatorial logics
<TS-Labs>
4 or 5 summators of different sizes
<mwalle>
so its likely that this will be the critical path :)
<TS-Labs>
yeah )
<TS-Labs>
i used 40 mhz, worked ok, but i didn't measure its latency
<lekernel>
multiply isn't part of the 'classic' instruction set
<lekernel>
(and btw modern synthesizers can pipeline '*' in verilog)
<larsc>
mwalle: I finally managed to get OpenWrt to build bootable images :)