<kristianpaul>
"You may not (and may not allow anyone else to) disclose the results of any benchmarking of a Licensed Product (whether or not the results were obtained with assistance from [the EDA vendor]) to any third party" patetic
<kristianpaul>
lekernel: can i say dma is mm soc is an implementation of a wishbone swich topology, and of course the cpu is the master 1?
<kristianpaul>
morning btw :-)
<lekernel>
it's a multi-master wishbone with (partial) crossbar switch
<Fallenou>
lekernel: is fml crossbar switch or pipeline or shared bus ?
<Fallenou>
topology
<lekernel>
hmm
<lekernel>
what would be the point of a crossbar?
<Fallenou>
I don't even understand the crossbar
<Fallenou>
it's just to know which one it is
<lekernel>
well, then read up on crossbars first, then ask yourself how many slave peripherals there are on FML and this should answer your question
<Fallenou>
I thought I could have a quicker answer here, obviously a mistake
<lekernel>
crossbars allow simultaneous communication between different masters each talking to a different slave
<Fallenou>
ok
<lekernel>
here there's only one slave, the sdram controller
<lekernel>
so it's obviously a shared bus
<Fallenou>
ok thanks
<terpstra>
is lm32 support in mainline gcc now?
<Fallenou>
it's been in mainline gcc for some time now
<Fallenou>
it's not recent
<lekernel>
it was thrown into gcc 4.5 without much advertisement
<terpstra>
great
<lekernel>
maybe I should update the gcc website myself :)
<Fallenou>
it's been two years ? something like that ?
<lekernel>
i'm just a bit afraid of using CVS and breaking things...
<lekernel>
one year
<Fallenou>
ok
<lekernel>
we also have serious issues with the C++ compiler - it seems to generate broken code in 4.5.x and no longer builds in 4.6
<Fallenou>
even the gcc-core-4.5.2 from rtems.org with their patch ?
<Fallenou>
it's generating kroken code ?
<Fallenou>
broken*
<lekernel>
yes
<lekernel>
at least it seems so
<terpstra>
lekernel, the g++ i have from lattice works
<lekernel>
I ran into the Qt4 broken method table bug with that one, and Till also had broken code issues
<terpstra>
though i've not built large programs with it
<lekernel>
but it's 3.x, no?
<lekernel>
or a modified 4.4
<terpstra>
its 4.3.0
<lekernel>
yeah ok :)
<lekernel>
gcc seems to be such a mess to maintain, they regularly break stuff... :(
<lekernel>
especially "minor" architectures
<Fallenou>
I guess they don't even test those minor architectures
<Fallenou>
do they even have testsuites for those ?
<lekernel>
iirc someone spoke about a gcc build farm on the ML... somewhere around July 2009
<lekernel>
I should contact him back to add some lm32 tests, even basic (just check that the compiler builds) to his suite
<Fallenou>
Examples for this are plenty. Many of the GNU projects are ported to a wide variety of platforms, even to undeserving once like cygwin and mingw
<lekernel>
free software isn't exactly the ideal world some advocacy organizations depict :)
<Fallenou>
yeah it seems so
<Fallenou>
lol Xilinx was routing power to blockram even if the blockram block was un used
<Fallenou>
they started to stop powering unused blockram in the 7 serie
<Fallenou>
30% of the power leakage was coming from unused blockram :)
<Fallenou>
let's turn off the light please if you don't use it !
<lekernel>
hmm???
<lekernel>
from what I can tell, leakage power in current FPGAs isn't that big anyway, so there can be a justification for that :)
<lekernel>
also, 28nm would leak more
<Fallenou>
well they are saying 28 nm is leaking less
<Fallenou>
Learn about the power benefits of the 28nm process Xilinx 7 Series #FPGA in this NEW white paper. http://bit.ly/WP28nm <=
<lekernel>
probably B.S.
<Fallenou>
lol
<Fallenou>
anyway, funny that they just happen to think about not powering what's not used by the design
<lekernel>
what it could mean is the leakage power per transistor is lower, but *all* the power per transistor is lower in 28nm, including dynamic power
<lekernel>
but the leakage/dynamic power ratio grows as process geometries shrink
<lekernel>
if they reduced it, it's not by switching to 28nm
<lekernel>
this actually makes things worse
<Fallenou>
humm ok
<lekernel>
btw, it'd be fun to get kintex7 support in llhdl before they generally sell the devices =]
<lekernel>
the reverse engineering process should be largely automated, and k7 isn't very different from s6
<lekernel>
so once s6 works great, supporting k7 should be a walk in the park
<Fallenou>
18:44 < lekernel> btw, it'd be fun to get kintex7 support in llhdl  before they generally sell the devices =]
<Fallenou>
LOL
<kristianpaul>
hehe
<Fallenou>
they could be very happy about that
<Fallenou>
I hope they will
<Fallenou>
or they could wake up a bunch of lawyers :)
<kristianpaul>
at least us will be happy :-)
<kristianpaul>
or they can offer a big fat job to lekernel ;-)
<kristianpaul>
ergg, ignore fat
<kristianpaul>
lekernel: are curently automating reverse eng process for s6?
<Fallenou>
his code parse Xilinx big fat information files about s6 arch
<kristianpaul>
I was thinking in ulogic actually
<scrts>
heh :)
<scrts>
I have a friend that is able to crack any altera megacore
<scrts>
which is encrypted
<scrts>
maybe someone did that for xilinx cores?
<Fallenou>
scrts: ask lekernel he told me about some xilinx core decryption one day
<Fallenou>
the key was somewhere distributed with the ise
<scrts>
well, for altera cores decryption the core ID is needed only
<scrts>
like 4 symbols code
<Fallenou>
lol
<Fallenou>
and then you get the all hdl source code ?
<kristianpaul>
netlist he get i think
<scrts>
yes
<scrts>
the source is available with quartus
<scrts>
it is only encoded
<scrts>
run the decoder and get the verilog files
<scrts>
move them to the altera ip core dir
<scrts>
regenerate the core
<scrts>
and no time limits :)
<Fallenou>
hehe :)
<Fallenou>
I never used encrypted core before
<Fallenou>
they have time limit ?
<scrts>
yep, works ~1hour in silicon
<Fallenou>
o_o
<Fallenou>
must be a big register to hold that much time information
<scrts>
hmm, I am not sure
<kristianpaul>
you can make a clock div and count cycles
<scrts>
afaik it is counted @ pc, because when You disconnect the jtag the core stops
<Fallenou>
well how do you know the clock freq ?
<Fallenou>
oh
<Fallenou>
ok
<Fallenou>
it sucks :(
<Fallenou>
is it the same with Xilinx closed-source IP ?
<scrts>
dunno
<scrts>
I use xilinx at home and altera at work
<scrts>
never used closed source xilinx cores
<Fallenou>
Has your friend written a blog post about that ?
<kristianpaul>
used to work with nios
<scrts>
the cores needed @ work were SDI based
<Fallenou>
SDI ?
<scrts>
serial digital interface
<scrts>
video standard :)
<Fallenou>
oh ok
<scrts>
mostly used in professional studies
<Fallenou>
didn't know this interface
<lekernel_>
scrts: I can also crack Xilinx encrypted IP, but there is nothing really interesting in there
<lekernel_>
and it's not even hard to crack
<lekernel_>
it's also illegal to use them... which makes it even less interesting
<Fallenou>
lekernel_: do you have the source of your slides of 26C3 ?
<lekernel_>
mom, I'm not sure... maybe lost them in a hdd failure last year
<Fallenou>
I am rewritting some pages since I don't have the source code
<Fallenou>
would help me :)
<Fallenou>
ooh too bad
<Fallenou>
otherwise I can continue rewritting
<lekernel_>
I have the sources of the university conference last month though
<Fallenou>
Once an organization has had its application accepted, anyone who has created a site wide profile can apply to that organization as a mentor
<lekernel>
well they do ask for an initial mentor list
<Fallenou>
oh ok
<lekernel>
and probably attribute slots based on that
<lekernel>
actually, they ask tons of stuff and writing an application is a pain
<lekernel>
especially when they reject it with an automatically generated message
<Fallenou>
slots are attributed after student proposals
<lekernel>
and accept shitty projects like beagleboard instead
<Fallenou>
so I guess they take into account the total number of mentors
<Fallenou>
yes it's not perfect
<Fallenou>
but it's still a good thing, if it can provide debugguer or mmu :)
<Fallenou>
how many mentors do you have lekernel ?
<Fallenou>
I guess there is mwalle + you , and then who else ?
<lekernel>
maybe Eric Rannaud (one of the ulogic guys actually ;) and Jon