<scrts>
I wonder what artix and kintex devices will be :)
<lekernel>
probably even buggier than s6
<lekernel>
it's amazing how crippled the s6 is... silicon bugs with BRAM asynchronous clocking, silicon bugs with BRAM initialization, and others, and they said they will NOT fix them
<lekernel>
given how rushed up the 7 series seems to be, i expect the worst
<lekernel>
i'd much prefer to see a "s6-stable" device than a freaky "k7"
<kristianpaul>
bram > buffer > fixo rx overflow  !! (That hapen just when doing pld load of the milkymist soc bitstream)
<lekernel>
oh, and no characterization of the IODELAY timing too... "let's shift the 45nm process problems to our customers"... that's why I had lots of intermittent DRAM problems on the M1
<lekernel>
terpstra: don't Altera multiplier blocks have internal pipeline registers?
<lekernel>
it seems weird to me that you have to split the operation manually
<methril_work>
lekernel, when you work in the USB part, do you thinks some usuall mistakes  that i could translate to CAN Bus?
<CIA-94>
milkymist: Sebastien Bourdeauducq master * r4c314c5 / (2 files in 2 dirs): Bump SoC version number - http://bit.ly/hnY3Iv
<CIA-94>
milkymist: Sebastien Bourdeauducq master * r5366fec / software/bios/main.c : Use timer for boot timeout - http://bit.ly/houF37
<lekernel>
seems they can't characterize a 45nm chip (IODELAY data mess + bugs in the timing analyzer) so those 28nm ones will be a disaster
<Fallenou>
is it so difficult to get the IO timing ?
<lekernel>
the I/O thing I'm talking about is:
<lekernel>
in S6 they introduced a new low-cost way to delay all incoming signals on every I/O pin
<lekernel>
on previous fpgas, it was done using a delay chain with a variable tap, and it included some calibration circuitry that worked great
<lekernel>
it was only available in virtex though
<lekernel>
in S6, they replaced that with a multi-GHz ring oscillator that drives programmable counters that generate the delayed signal when they overflow
<Fallenou>
hum ok
<Fallenou>
sounds great too
<lekernel>
the problem is the frequency of said ring oscillator is totally unstable
<lekernel>
and your delays vary by a ridiculous margin, some 1000%Â Â (can't remember the exact figure from the datasheet, but it's a total mess)
<lekernel>
and you can't easily calibrate them
<lekernel>
they removed the previously available calibration logic that compared the delays against a reference clock
<lekernel>
and allowed you to have precise delays without much of a mess
<lekernel>
I think my next FPGA design will have an Altera chip
<lekernel>
Fallenou: it's not in the UCF, IODELAY2 is a logic primitive you instantiate in the signal path to (hopefully) implement the programmable delay
<Fallenou>
oh ok
<Fallenou>
I remembered something about "delay" in the ucf
<Fallenou>
that you can put on the pins of the fpga
<Fallenou>
oh ok it's the SLEW
<jackgassett>
hello, I was just checking out the Softusb project and was wondering what was used for synthesis.
<jackgassett>
I tried with Xilinx ISE and it gives some errors.
<lekernel>
phew, LZMA decompression is slow as hell... boot time went from 9s to 43s
<lekernel>
jackgassett: well right now there aren't that many options. we use ISE too
<lekernel>
softusb cannot be used stand alone
<lekernel>
I don't know what you tried to do...
<jackgassett>
ok, so it probably just needs some love then.
<jackgassett>
I just wanted to see if it should work with ISE.
<lekernel>
if you just take the contents of the softusb/rtl folder and drop that into an ISE project, there's no chance it would work
<jackgassett>
ok, so it looks like memory needs to be added through wishbone bus then?
<lekernel>
memory is integrated
<jackgassett>
and then peripherals can be added with your csr bus?
<lekernel>
well, have a look at the ports on the top level
<lekernel>
(softusb.v)
<jackgassett>
ok, right I see that memory is included, Data and Program.
<jackgassett>
I commented out the sie and hostif modules because I just wanted to check out navre and wishbone controller for now.