<kristianpaul>
lekernel: you made this crossbar swich and conbus motifications because navre? if, yes why?
<kristianpaul>
install gitg in order to do a better browsing of changes
<Fallenou>
hehe gitg is great
<Fallenou>
gitk too
<Fallenou>
something funny is gource
<kristianpaul>
wow
<kristianpaul>
gource is awesome
<kristianpaul>
(not saying how usefull)
<kristianpaul>
the little human moving and jumping around is sebastien? :_)
<Fallenou>
its not written "lekernel" on it ? :p
<kristianpaul>
oh yes
<kristianpaul>
finally clicked on it
<kristianpaul>
is moving fast
<Fallenou>
oh my gource is broken
<Fallenou>
gsoc organization applications are now closed
<Fallenou>
I hope we submitted
<kristianpaul>
lets wait rejon
<kristianpaul>
ok xbar is the new conbus
<lekernel>
Fallenou: rejon submitted it, yeah
<lekernel>
kristianpaul: what jumpy person?
<kristianpaul>
jumpy?
<kristianpaul>
i used word jump for when some one will join something
<kristianpaul>
may be is not well miss undernstoof for the enlgish concept
<kristianpaul>
zzz
<kristianpaul>
Fallenou: remenber MLEN it was defined in ./cpukit/libnetworking/sys/mbuf.h but it you already knew it..
<kristianpaul>
Fallenou:About ethernet driver, where are defined DMA "parameters" wich point the right address from system memory to read?
<kristianpaul>
Is that the procedure isnt?
<kristianpaul>
or wait, question is how to you read the the rx slots
<kristianpaul>
?
<kristianpaul>
thinks that have a misscopnception about DMA
<kristianpaul>
ah i fount somethin..
<kristianpaul>
found*
<kristianpaul>
0x0C 0x18 0x24 0x30 are slots DMA adress
<kristianpaul>
rtfm
<kristianpaul>
hmm but thosre are adress at the CSR bridge..
<kristianpaul>
let see
<kristianpaul>
acording to system_conf.h  MM_MINIMAC_ADDR0 0xe000800C
<kristianpaul>
Peripheral                      WB base (L1 cached/uncached)
<kristianpaul>
FML bridge (SDRAM)Â Â Â Â Â Â Â Â Â Â Â Â Â Â 0x40000000 / 0xc0000000
<kristianpaul>
ah !
<kristianpaul>
ergg no
<kristianpaul>
CSR bridge                      0x60000000 / 0xe0000000
<kristianpaul>
but from xbar
<kristianpaul>
// SDRAMÂ Â Â Â Â Â Â Â 0x40000000 (shadow @0xc0000000)
<kristianpaul>
argg again
<kristianpaul>
// CSR bridge  0x60000000 (shadow @0xe0000000)
<kristianpaul>
Fallenou: when you read MM_MINIMAC_ADDR0, this reg store an adress not actually data?
<kristianpaul>
lekernel: resuming, can you explain me a bit how is implemented the DMA Controller in the mm1 soc?
<kristianpaul>
if there is one..
<lekernel>
well just send wishbone or fml master cycles?
<lekernel>
cores supporting dma are simply additional bus masters, whose requests get routed to the peripherals through the arbiters
<lekernel>
there's no special DMA infrastructure (yet)
<kristianpaul>
ah
<kristianpaul>
hmm, so potentially devices like the ethernet core can create bottle neck in for busy env on wich the ethernet handle big amount of data..
<kristianpaul>
of course not the case for a VJ ;-)
<lekernel>
you have this problem with any centralized shared memory system
<kristianpaul>
is the case also of fml? (note i dint read too much about this yet)
<kristianpaul>
s(¿/of/for
<kristianpaul>
oops
<lekernel>
yes, of course
<lekernel>
but fml has higher throughput than the wishbone bus
<kristianpaul>
so, the swich code you added with the cross bar will help on this shared bus problem, isnt? but is working right now?
<lekernel>
all the crossbar allows is simultaneous processor<->flash (which uses the bus inefficiently due to the flash's slowness) and ethernet<->ram communications
<lekernel>
this way the processor<->flash communication, e.g. when running the bios, doesn't suck all the memory bandwidth from the ethernet core
<kristianpaul>
if the pfpu is not in the fml,  it means the caculations it have are no so troughtput demanding? or..
<kristianpaul>
(ethernet<->ram communications) ah. nice hint ! less fifo overflow issues ;-)
<kristianpaul>
s/fifo/buffer
<lekernel>
well, I'll leave it as an exercise for you to compute how much memory bandwidth the pfpu is using
<kristianpaul>
;-)
<kristianpaul>
If you're are teacher i wish the best for your students
<lekernel>
oh come on, it's not hard
<kristianpaul>
But if remenber well you compile the pach before run it..
<lekernel>
two 32-bit integers on each vertex of a 128x128 grid, 30 times per second, how much bandwidth is that?
<kristianpaul>
1 megabyte per second i think
<kristianpaul>
but i may wrong i dont know what the vertex part is about in the rendering process
<kristianpaul>
but i guess (128*128*30)*2
<lekernel>
*32
<kristianpaul>
oh, yes i asumed data word byte but is a integer, true
<Fallenou>
kristianpaul: yes the reg stores address
<kristianpaul>
Fallenou: yeah ;-) oh well i still learning :-)
<kristianpaul>
lekernel: Fallenou mwalle  wpwrak  What you think about http://sphinx.pocoo.org/ in order to create a central base for milkymist soc documentation
<kristianpaul>
That could be esilly update rather than individuals pdf.. latex...
<kristianpaul>
of course that, project is not a wiki, and should be friendly for programmers
<lekernel>
personally, even though I recognize the value of documentation (and I think milkymist has second-best documentation for open source SoCs after GRLIB), I have little time to take care of it...
<lekernel>
note that this doesn't mean i'm against switching to sphinx, just that it's not high on my priority list
<kristianpaul>
oh, sure, i just asking if you like this platform or have suguestions for other?
<kristianpaul>
migration could be done even slowly, but wiki could be a good point for decent manuals, also pdf is not easilly updated within the time
<kristianpaul>
wiki could not*
<lekernel>
well, at first sight it looks better than doxygen
<Fallenou>
kristianpaul: it seems great
<Fallenou>
for the moment we have a wiki, which is good too
<Fallenou>
I think we can first focus on writing some valuable documentation on the wiki
<Fallenou>
before thinking about migrating stuff to another plateform
<Fallenou>
but yes it looks nice :)
<Fallenou>
wiki pages looks nice too imo
<kristianpaul>
lekernel: Are you aware of a way/program to convert verilog to a DOT graphiz output?
<lekernel>
no
<wpwrak>
kristianpaul: (doc) dunno. i find post-processing-friendly comments in source code hard to read.
<lekernel>
kristianpaul: also, DOT would be a mess with large and complex verilog files
<lekernel>
and maybe not even relevant
<lekernel>
it works great for LLHDL to show the tree like structures (which e.g. can help explaining/understanding how libmapkit plug-ins work) but for verilog...
<kristianpaul>
lekernel: yeah in llhdl looks awesome
<kristianpaul>
(relevant) indeed, actually as the DOT ouput should be done after the sintesis process i think
<lekernel>
as you can see, it doesn't work so well except for designs of trivial complexity
<kristianpaul>
puff, what a mess
<kristianpaul>
remenber when trying to undesrstand some self generated networks maps by ntop + graphiz
<kristianpaul>
now i read with care sebastien tesis i'm please to read how a FFT process done by software on a PC is replaced by an accumulator :-). So the new zelands were not so crazy after all when they tought that for the gold code tracking
<kristianpaul>
Fallenou: how big a ethernet frame is?