<carlobar>
hi, i have modified the the HPDMC controller in order to support 16 bits memories, but i got errors and i dont know whats wrong.
<carlobar>
The HPDMC write/read 16 bit data, so i made an entity that perform 2 read/write to get a 32 bit data.
<carlobar>
I can read/write data using the bootloader, but when i try to write at 0x40002000, the data at 0x40000000 is overwriten, and i dont understand why. I made a simulation of a write operaion at 0x40002000, but it looks fine, someone can help me?
<kristianpaul>
hmm, icap allows multiboot
<kristianpaul>
but is not clear to me if xilinx support partial reconfigurarion or core load/unload.. in spartan6..
<kristianpaul>
all what i found is about virtex
<kristianpaul>
multiboot still nice, but not the main goal..
<kristianpaul>
well, if you can resume and reboot fast enought... ;)
<kristianpaul>
"current implementation of the bus macro uses eight 3-state buffer" ohh, 3 state
<kristianpaul>
and saying, okay i can do reconfigure  partially, it will be not much that two "modules" it seems..
<kristianpaul>
bah, i forgot check  ack before read wb_data_i ..
<lekernel>
carlobar: see fml doc, you need an uninterrupted stream of data, which means your hack cannot work unless you also double the DDR frequency
<lekernel>
(you can also just buy a M1 *g*)
<lekernel>
kristianpaul: partial reconfiguration works for spartan6, but as always it's bloody and dirty
<lekernel>
it doesn't use 3 state buffers though (the s6 doesn't have them anyway)
<lekernel>
and you can have as many modules as you want (or, more exactly, 1/16 of the FPGA tile count on S6, but that's a lot :p) but you have to be prepared to hack the tools and/or the bitstream files quite heavily for that, depending on how much flexibility you need
<kristianpaul>
lekernel: (partial reconfiguration in s6) how do you know that? already tried? got some paper about it? or..
<lekernel>
i'm using the partial reconfiguration features to reverse engineer the bitstream format more easily
<kristianpaul>
:o
<kristianpaul>
ha, cheating, you are taking apart the bistream  using partial reconf!
<kristianpaul>
make sense
<lekernel>
jeje
<kristianpaul>
(it doesn't use 3 state buffers though) so, what it uses?
<kristianpaul>
a special secret xilinx unviversal bus? :p