<kristianpaul>
sure i know is cross clock domain, but i wast aware if this kind of implementation..
<kristianpaul>
reads
<lekernel>
wolfspraul, this is hopefully subject to change with FPGA design upgrades, so don't write it all over the marketing material
<lekernel>
kristianpaul, the full minimac2_psync is well explained on the fpga4fun website
<kristianpaul>
ok
<wolfspraul>
no worries. first I need to understand where it is today, what is realistic with updates, what is the theoretical maximum of the current hardware
<wolfspraul>
that's important in many ways, for customers, also for potential contributors, etc.
<wolfspraul>
all fine, I think it's all great
<lekernel>
if we get to do the "pro" version i'll probably make a new soc architecture to support 30bpp 1280x1024 everywhere (or something like that)
<lekernel>
with improvements such as switching to myhdl, new bus architectures, faster memory controller, faster texture mapping unit, multiple LM32 cores, etc.
<lekernel>
as I said, lots of work
<kristianpaul>
(myhdl), :o
<kristianpaul>
"get to do the "pro"" you mean, basically is a funding problem?
<lekernel>
partly, it's also a problem of finding customers for it
<kristianpaul>
just to be sure, that 'pro' word scare me a bit from before projects i know ;)
<kristianpaul>
sure
<kristianpaul>
yeah, sure you are the experts about recomended specs for VJing stuff
<kristianpaul>
ha, flags i missed that part :-)
<mumptai>
hi
<lekernel>
hi
<GitHub143>
[milkymist] sbourdeauducq pushed 1 new commit to master: http://bit.ly/pKALxU