<GitHub179>
[board-m1/master] added .gitignore file - Adam Wang
<wolfspra1l>
cladamw: good morning!
<cladamw>
good morning :)
<wolfspra1l>
everything alright on your end? do you need any help?
<cladamw>
no need now. :-)
<wolfspra1l>
ok good
<cladamw>
1. I'll create initial Hierarchical Sheet for M1, it means to include all schematic empty sheets firstly
<cladamw>
2. since the house sent me file already, so after hierarchical sheet, I'll back to review the placement then feedback to them if there's things that we dislike, then i back to continue edit board-m1
<wolfspra1l>
what did plab send you?
rejon has joined #milkymist
<cladamw>
design files( I'll check .PcbDoc for placement and their footprint files )
pablojavier has joined #milkymist
pablojavier has quit [#milkymist]
xiangfu has joined #milkymist
<wolfspra1l>
can you export and upload a gerber? maybe we can try to compare a little with rc3 using gerbv :-)
<cladamw>
[current task] I'm doing the review/confirmation of new pcb footprints.
fpgaminer has joined #milkymist
mumptai has joined #milkymist
wolfspraul has joined #milkymist
voidcoder has joined #milkymist
<wpwrak>
cladamw: how can i view MILKYMISTONE.PCBDOC ?
<wpwrak>
"file" says "CDF V2 Document, No summary info"
<wpwrak>
and libreoffice gives me a very long list of possible choices
<cladamw>
wpwrak, so far i don't know how to let you review directly from .PCBDOC .:)
<cladamw>
it's not completely finished on placement
<wpwrak>
can AD "print to PDF" this ?
<cladamw>
the most are for me now is to review/confirm footprint (filename = MILKYMISTONE.PcbLib)
<cladamw>
moment
<wpwrak>
(or maybe even "export to gerber" ? :)
<cladamw>
i can export to pdf
<cladamw>
then you can select part
<wpwrak>
PDF would be great. MILKYMISTONE.PCBDOC has the placement, right ?
cladamw_ has joined #milkymist
<cladamw>
yes, but not initial placement, it just we called "NET-IN" only. :)
<cladamw_>
while NET-IN results from house, i started to review/confirm the footprint via *.PcbLib file, not .PcbDoc
<cladamw_>
this net-in version was house sent to me after one week. so they are still working on the expansion J21/J22 placement, but in this version. It hasn't finished.
<cladamw_>
Regards to how export *.PcbLib, i don't know at all. But from AD library viewer I can one-by-one to check. It's more the check/detail on comparing datasheet/drawing.
stekern has joined #milkymist
<cladamw_>
[Fped] is the tool to build library. (i.e.) same house firstly to edit footprint for us. then confirm with us. (this stage as the KiCad of M1r4 to be as review stage as footprint review call)
<cladamw_>
(i.e.) most here what houses are doing.
<cladamw_>
in om, this job were confirmed by layout guy only. not by EE to confirm each footprint, this reason caused many troubles made.
<cladamw_>
wpwrak, I'll go house again since that for placement goal. so if you spot any potential problems, let me know.
<wpwrak>
(no review at OM) heh ;-)
<cladamw_>
wpwrak, liked I said the current pdf genenrated is only for reference. Haven't not drag all parts withing boards. fyi.
<wpwrak>
(looking at the PDF) ah, so that's already a parial laout
<cladamw_>
but the pdf file you can see them. yeah..
<wpwrak>
(not all parts) yes, i can see them on the right ;-)
<cladamw_>
EEs in om were reviewing layout/routings mostly, i almost not see how they review footprints reviews.
<cladamw_>
yeah
stekern has joined #milkymist
<cladamw_>
sorry that i was for PE not EE, not responsible for HW manager can let me worked them. :-) I can head up only. :-)
<wpwrak>
(PE) yuck
<cladamw_>
i just reviewed DVI-I footprint, it's perfect same as datasheet though. :-)
<wpwrak>
looks pretty much like M1rc3 so far
<cladamw_>
few questions: for expansion board
<cladamw_>
1. (height) the relationships between IR.
<cladamw_>
2. J3/J23/J26, they are DNP, and close to the area of expansion board., this is to be done, I'll let house to place sourrounding expansion area. Are you okay ? after that we determine ? or we define them from ourselves firstly ?
<wpwrak>
height is given by the connectors. i.e., female header + male header, combined height
<cladamw_>
yeah...i knew it.
<wpwrak>
should usually be something like 10-11 mm
<wpwrak>
that is, the distance between main PCB and the bottom of the expansion board's PCB
<wpwrak>
(J3 etc.) yes, i'd leave them to the layout house. see what they come up with. they're more like "just in case" anyway. i don't think we should even guarantee that they'll be at the same place in the future
<cladamw_>
total height = J21(female, 8.5mm) + e.g. expansion board thickness (1.6mm) + male header(2.54mm) = 12.64mm , just to confirm that do you have any further placement for IR ? Since the height of IR can be under that area. :-)
stekern has joined #milkymist
<cladamw_>
yeah...so I meant (i.e.) I would let house to move wherever house wants. :-) Do you agree ?
<wpwrak>
yes
<cladamw_>
good
<cladamw_>
so would you do me a favor for drawing the specification for like an "limited height area" under expansion board ? or we do this later after we/house settle the placement done ?
<wpwrak>
i would ask the layout people to keep tall parts out of that area in general
<wpwrak>
then we can define the exact profile based on the final layout
<cladamw_>
ha...that's the guidline one rule but not must. good idea. :-)
<wpwrak>
if they need to put tall parts under the expansion board area, they should be near the edge of that area
<cladamw_>
depends on parts function. :-)
<cladamw_>
okay
<wpwrak>
i.e., i wouldn't want to see a 0.95 mm cap right in the middle :)
<wpwrak>
err. 9.5 mm
<wpwrak>
0.95 mm would be fine ;-)
<cladamw_>
hehe...yeah..it'll destroy power of expansion board.
<wpwrak>
i think we may overlap a bit with the DVI connector in the lower right corner
<wpwrak>
err, lower left
<wpwrak>
(lower left of the expansion board)
<wpwrak>
sigh. my brain isn't working too well these days :-( enjoying a flu. so if i sound confused, that's why
<cladamw_>
btw, actually the height is 8.5mm + 2.54mm = 11.04mm, a normal pin header's mating length is for example 5.84mm, so J3/J23/J26 can be under expansion area, but it's not good idea for pull out. so i would also let house to place them surrounding area.
<wpwrak>
yes, the best place would be to have them something like 1 mm outside of the expansion board area. that way, one easily make an "extended" board with connectors for them, too
<cladamw_>
(outside 1 mm) okay...
<cladamw_>
(J17) lower left ? sorry can you describe again ?
<wpwrak>
(J17) hmm, looking at it again, it may actually not overlap.
<wpwrak>
yeah. should be clear. false alarm, sorry
<cladamw_>
alright. :-)
<cladamw_>
(U10/U11/U13) power regulators i'll move them lower a bit since we may need to solve the difficulty of current right-angle usb plug doesn't easiler to insert jtag/serial board.
<cladamw_>
which means the routes of current power area may be changed a lot but I leave this to be the last task one. since it means the relationships between jtag/serial board and 8:10 card will be moved a little.
<cladamw_>
but like i said I leave this to be last task, since DVI-I routes are #1. :-)
<cladamw_>
wpwrak, follow me ?
<cladamw_>
wpwrak, i go for dinner first, cu
<wpwrak>
we give no guarantees with regard to jtag vs. 8:10 anyway
elldekaa has joined #milkymist
lekernel_ has joined #milkymist
elldekaa has joined #milkymist
voidcoder has joined #milkymist
cladamw has joined #milkymist
<wpwrak>
(moving jtag) we give no guarantees with regard to jtag vs. 8:10 anyway
<wpwrak>
afk for a few hours now
voidcoder has joined #milkymist
<wpwrak>
and back again
<wolfspraul>
wpwrak: pah too many things in parallel
<wolfspraul>
do you have any feedback regarding adam's kicad-m1 work?
<wolfspraul>
I can't keep track of the backlogs right now
<wolfspraul>
it looks like he is charging ahead, looks good...
<wolfspraul>
I upleveled the cmdline patches recently btw, just to stay fit
<wolfspraul>
it's easier to catch the inevitable stream of renames in short bursts than too many lumped together
<wpwrak>
wolfspraul: what he's doing looks good so far. except that he's lumping many components in a single file. that's a structure encouraged by kicad, but it means that the revision control system works poorly
<wpwrak>
(uplevel) yes, saw it. very good, thanks !
elldekaa has joined #milkymist
hypermodern has joined #milkymist
<wolfspraul>
wpwrak: so adam should just continue on the current path for now?
<Fallenou>
most of the time it's trying to access page 0
<Fallenou>
only 2 tests are correct !
<Fallenou>
bbl
qwebirc35069 has joined #milkymist
<wpwrak>
Fallenou: hmm, even the addresses with the upper bits the same differ in the lower bits: 0x44002024 - 0x44001024 = 0x1000
voidcoder has joined #milkymist
voidcoder has joined #milkymist
kilae has joined #milkymist
kyak has joined #milkymist
Gurty` has joined #milkymist
<Fallenou>
wpwrak: those are correct I was mapping 0x44002000 to 0x44001000 :)
<Fallenou>
dont take my small victory away from me :'
<wpwrak>
ah, good :)
<Fallenou>
so now its clear why it crashes => access to page 0
jpbonn has joined #milkymist
<Fallenou>
I need to figure out what timing I have wrong
<wpwrak>
(page 0) ah yes. that explains it nicely
<lekernel>
Fallenou: if you want to synthesize faster, you can edit setup.v and disable the cores you don't need
<lekernel>
I see you still have all of them enabled
<lekernel>
if you disable the TMU the BIOS will nicely switch to software scrolling btw
voidcoder has joined #milkymist
<Fallenou>
21:52 < lekernel> Fallenou: if you want to synthesize faster, you can edit setup.v and disable the cores you don't need < good idea, thanks !
<Fallenou>
8 minutes !
<Fallenou>
nice :)
<Fallenou>
instead of 20/25 min, and still booting bios and running the tests
<mwalle>
lekernel: do you think its possible to run the navre core at 72mhz ?
voidcoder has joined #milkymist
<lekernel>
probably
<mwalle>
how would you do it? two clocks? one clock and ce?
<lekernel>
it's already one clock and ce :) keep the same design and just adapt the ce generator
<lekernel>
if you want you can simply CE the CE generaot
<lekernel>
generator
<lekernel>
then going back to 48MHz is just a matter of connecting that CE to 1
<mwalle>
lekernel: so for the tx side its the gce and for the rx side its the dpll_ce right?
<lekernel>
(of course you need to combinatorially AND the generated CE with the generator's CE)
<lekernel>
yeah
<mwalle>
(well the ce for the dpll, not the dpll_ce)
<lekernel>
you can try first to set the DCM to 72MHz and check that it still meets timing
<lekernel>
ah, and there's also fs_timeout_counter you need to increase (or CE)
<mwalle>
lekernel: mhh is there a way to make 72mhz from 50 with one dcm?
<mwalle>
maybe theres some trick to double the frequency? :) because the synthesizer only allows max multiplication of 32
sh4rm4 has joined #milkymist
<lekernel>
you can use a PLL instead which supports more ratios
<mwalle>
th
<mwalle>
thx
<mwalle>
mh 400MHz < Vco < 1000MHz
dvdk has joined #milkymist
voidcoder has joined #milkymist
lekernel_ has joined #milkymist
wolfspraul has joined #milkymist
<wpwrak>
wolfspraul: (continue) yes. he's also learning to use the tools, familiarizing himself with some of the quirkier bits, which is good
<wolfspraul>
ok, but I want to focus fo finish the transfer asap :-)
<wolfspraul>
already getting anxious to get the bom going, and maybe even peek into layout - why not...
<wolfspraul>
s/focus fo/focus to/
<wpwrak>
regarding layout, it would be good if we could get what adam has from the layout house so far in gerber. that way, it's possible to help with reviewing the footprints
<wpwrak>
the PDF alone isn't very convenient for checking geometry
<jpbonn>
I'm trying to use flterm without success. Is there a pre-built binary I can download and run?