01:20 <GitHub175> [board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/2fb456ae7bf6be5497f005de46c462f23ce093df

01:20 <GitHub175> [board-m1/master] linked to rca.lib - Adam Wang

02:58 <GitHub130> [board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/9dcb160226933c10e1f39fae7a91dfbad0ae8346

02:58 <GitHub130> [board-m1/master] Ethernet.sch done - Adam Wang

07:25 <GitHub5> [board-m1] adamwang pushed 2 new commits to master: https://github.com/milkymist/board-m1/compare/c2eb540...3a0aebf

07:25 <GitHub5> [board-m1/master] chips added in - Adam Wang

07:25 <GitHub5> [board-m1/master] Merge branch 'master' of github.com:milkymist/board-m1 - Adam Wang

09:20 <GitHub190> [board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/d41937049215e3d60e31b8c3a4542e55407ee4ed

09:20 <GitHub190> [board-m1/master] rough done on Power.sch - Adam Wang

09:33 <GitHub164> [board-m1] adamwang pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/a4c40c52d5b532dadb4632462628e5d9328c0f43

09:33 <GitHub164> [board-m1/master] from +3.3V to 3V3 - Adam Wang

14:38 <GitHub142> [board-m1] xiangfu pushed 1 new commit to master: https://github.com/milkymist/board-m1/commit/496d876fde2468df2a40a8b5984e4f5f9ca69093

14:38 <GitHub142> [board-m1/master] MISC: add J5/J6/J19 and memcard connector, change the comment from local label to real comment - Xiangfu

16:10 <lekernel__> jimmythehorn, hi :) learned about Milkymist at Notacon I guess?

16:11 <jimmythehorn> yep :)

16:11 <jimmythehorn> knew of it before, but never really had a chance to look into it

16:11 <jimmythehorn> and I rather enjoyed Sebastien's talk

16:16 <lekernel__> thank you ;)

16:21 <jimmythehorn> aha.... connecting irc handle to real world name, now, I think ;)

16:25 <lekernel__> azonenberg, http://www.youtube.com/watch?v=LG1kVIIy2Ok Particle Accelerator on a Chip

20:42 <lekernel__> wolfspraul, still have patience blocking mediawiki spam accounts? wow...

20:43 <mwalle> lekernel__: do you have an idea/trick how to pass needed information in a state machine apart from the state itself? eg simplify the RETIx states (see here http://paste.debian.net/163584/) and combine them with the normal RET/STALL states?

20:44 <lekernel__> sure, use a register

20:44 <mwalle> then clear in stall state?

20:44 <mwalle> that is, the last state i need that information

20:44 <lekernel__> you can write the register before entering RETI/RET/STALL

20:45 <lekernel__> and read it in any RETIx/RETx/STALLx state to alter the general behaviour

20:47 <lekernel__> (to write, you'll need something like a write enable and a data signal, since you are in a comb process. but I guess you know that already)

20:51 <mwalle> yeah thanks

20:52 <mwalle> btw i had a look at the blocking assignment inside navre

20:52 <mwalle> eg the writeback signal

20:54 <mwalle> do i get it right that converting that to NBAs you have to split it into comb and seq processes?

20:58 <lekernel__> no, you can get away with a seq process

20:59 <mwalle> so?

20:59 <mwalle> mind a little example? :)

21:01 <lekernel__> mom

21:01 <lekernel__> yes

21:02 <lekernel__> http://pastebin.com/Sa3Fxjhj

21:04 <mwalle> huh? mix blocking and non blocking assigments?

21:04 <wpwrak> what is the unary | called ? haven't noticed that yet

21:04 <mwalle> wpwrak: combining operator iirc

21:04 <lekernel__> that's what vhdl does when you have variables :) and afaik tools don't whine as long as those assignments target different signals

21:05 <lekernel__> reduction operator, it ORs all bits from the vectored signal

21:05 <mwalle> ah reduction :)

21:05 <lekernel__> you have a unary & too

21:05 <larsc> wpwrak: http://www.asic-world.com/verilog/operators2.html

21:06 <wpwrak> oh, handy. thanks !

21:08 <lekernel__> mwalle, note that in this example, you don't need the blocking assignment on v_bar - you can use bar directly, with a NBA

21:09 <mwalle> lekernel__: yeah sure, what i've missed was to mix both assignments in one block but not on the same signal :)

21:56 <mwalle> gn8