lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<xiangfu> have a question about GCLK pin. when I connect a osc to GCLK pin. the jtag because un-stable. for example on 'detect' and 'pld load ...'
<kristianpaul> s/because/become =
<kristianpaul> s/=/=
<kristianpaul> ?
<xiangfu> s/because/become
<xiangfu> sorry for typo.
<xiangfu> when I disconnect the GCLK pin. I can load bistream >20 times.
<xiangfu> when I connect the GCLK pin to osc. the pld load became un-stable.
<xiangfu> ~3 of 20 times can be success.
<xiangfu> kristianpaul, I have improve on my mini-jtag problem. now there must be hardware problem left.
<xiangfu> the GCLK I mean 'IO_L30N_GCLK0_USERCCLK_2' PIN55 of slx9 chip.
<Fallenou> is the osc "clean" ?
<Fallenou> is the frequency the "good one" ? (is there a precise frequency to have ?)
<xiangfu> not clean. I manually soldering the osc to a pcb. I have to connect the 2 power wires. then connect the clk wires back to fpga chip.
<xiangfu> the low osc get better result.
<xiangfu> any advice on making a stable osc ? for my mini-slx9 board
<xiangfu> the osc and fpga chip not on same PCB. :(
<xiangfu> I have to connect them by using a ~5CM wire.
<kristianpaul> wait the osc is alone?
<kristianpaul> 5cm is long
<xiangfu> yes. it's alone.
<kristianpaul> hmm some capacitors may be missing
<kristianpaul> by osc you mean a xtal?
<xiangfu> I mean 'crystal'
<xiangfu> 5CM wire is too long. maybe I try to use even low osc, like 32K.
<kristianpaul> but add tha caps
<kristianpaul> in paralle to the xtal ground
<kristianpaul> or it will not resonate well i think
<xiangfu> kristianpaul, I added 2 0.01uF caps to the power pins of crystal
<xiangfu> kristianpaul, the board is like: http://downloads.openmobilefree.net/tmp/mini-slx9-all.jpg
<roh> hm. maybe use a osc not an xtal... more stable with such long wires
<xiangfu> ok. I am a little confuse on osc and xtal. I know there are 4 pins and 2 pins type.
<xiangfu> (4 pins) crystal oscillate when apply a voltage.
<xiangfu> I am a little confuse on those two English wolds.
<roh> yeah.. they sometimes get mixed up, but i think you got it right
<roh> many devices can even work with both, but sometimes need correct config fuses to be set, like on avr or similar mcu
<xiangfu> s/wolds/words
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<roh> i see 2 small ceramic caps to ground on crystal in the area of 12pf-18pf on xtals and blocking caps of 10-100nF on the vcc of oscillators
<roh> theses osc are basically nothing but 2 inverters with a crystal, some caps and maybe a resistor in one case
<roh> for usecases where one has lots of load on a clock when for example multiple devices get the same clock from one source
<roh> but they are more expensive than a simple xtal of course
<xiangfu> in the top-middle pcb. there are 3 osc. each osc connect one cap. one of them connect a resistor. in that picture I am using a 20M osc.
<xiangfu> what should I do to improve the osc 'stable'? 1. using short wire. 2. using a low osc(like 32K etc) right?
<xiangfu> I really hope I can make any pcb like Werner does. :-D
<kristianpaul> :-)
<kristianpaul> yeah
<xiangfu> kristianpaul, ok. just switched to a short wires. it do get better.
<wpwrak> that was roughly what came to my mind when i saw your wire chaos ;-)
<wpwrak> at how many MHz is the osc running ?
<xiangfu> 20M
<xiangfu> (wire chaos ) that is my routing result without using KiCAD. :-D
<wpwrak> hmm, with your setup, that may already be too much. it's now only that you have very long signal wires but also that your ground is probably very complicated. e.g. the clock signal needs to "travel back" on ground somehow. and there's probably no direct way. so that's one thing to check: make sure you have FPGA ground and oscillator ground connected near the clock signal.
<wpwrak> you really ought to make your own pcb. that monster you've created may be okay for an arduino, but an fpga is a bit more complex :)
<kristianpaul> you can get made the one from azonenberg , i guess is cheap street work
<wpwrak> or use the design as a basis but simplify it first. the layout is somewhat demanding (and designed for high speeds)
<kristianpaul> yeah
<kristianpaul> simplify btw, if i delete footprints kicad deltec the un connected routes
<kristianpaul> thats a plus :)
<kristianpaul> deltec/delete
<xiangfu> I learned a lot by making those boards. :)
<kristianpaul> or just simply avoid the wires as much you can
<xiangfu> (make sure you have FPGA ground and oscillator ground connected near the clock signal.) hmm.. how do I do this in my wires project?
<kristianpaul> not use wires :)
<kristianpaul> connect all in same breakout board
<kristianpaul> near
<cde> longer wires can act as antenna, usually not good
<Fallenou> hehe :)
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<xiangfu> why the bad osc make jtag load bitstream un-stable?
<wpwrak> xiangfu: you could have a ground pin and a signal pin next to each other (on both sides). when connect them, ideally with a piece of ribbon cable (that way, you can have easily two wires next to each other)
<wpwrak> bad osc makes everything unstable :)
<wpwrak> and maybe it's not bad osc but bad voltage. or both. e.g., the decoupling caps for fpga power, are they on the same board as the fpga ? or are they on the other side of some wire ?
<xiangfu> those decoupling caps on the other side of some wire.
<xiangfu> wpwrak, (a ground pin and a signal pin next to each other) got it.
<wpwrak> that makes them useless. they should be millimeters away, not 10 cm
<xiangfu> :-)
<xiangfu> ok.
<wpwrak> xiangfu: it's not an introduction. it's rather a book that tells you what goes wrong after you've done everything the introductions tell you.
<xiangfu> wpwrak, I have read ~1000 pages English book (1.5 book, I should finish the second one). before start those work. now another ~500 pages book.
<wpwrak> sorry ;-)
<xiangfu> wpwrak, thanks for the link.
<cde> xiangfu: are those books also on circuit design? would you recommend them?
<xiangfu> more books always good. :-)
<wpwrak> but this is a good one. it's very hands-on. and it helps to understand some of the concepts others sometimes mention without properly explaining.
<xiangfu> wpwrak, the English book is hard for me. :-)
<xiangfu> cde, no. not on circuit design.
<wpwrak> for n -> infinity, diffculty of book n goes towards zero :)
<cde> ok
<xiangfu> cde, Digital_Design_and_Computer_Architecture
<xiangfu> the second one is 'Semiconductor_Manufacturing_Technology'
<xiangfu> wpwrak, :-)
<xiangfu> wpwrak, I will read that one. thanks
<xiangfu> wpwrak, I am writing the code that read the Configure Register Status out by using jtag. is there more registers that I can read by using jtag?
<xiangfu> wpwrak, (ug380.pdf P151: Configuration Register Read Procedure (JTAG))
<xiangfu> wpwrak, expensive book, compare to others.
<wpwrak> yeah. they seem to know its value.
<cde> thanks very much, xiangfu
<wpwrak> see pages 93, 102 of ug380
<xiangfu> wpwrak, thanks
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