lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<Fallenou> lekernel: DDR4 is this marketing bullshit or do we earn something by using that ?
<Fallenou> in term of real bandwidth
<Fallenou> I hope they don't increase latency
<lekernel> yeah, it should be faster
<lekernel> 3.2Gbps/pin is higher than the ~1.8 of DDR3, and with more banks and the new access scheme you should increase page hit rate and make transfers more efficient than normal bursts
<Fallenou> ok, great then !
<lekernel> of course, FPGA I/Os are still too slow to handle that *sigh*
<Fallenou> :/
<lekernel> if you want very fast memory look at the GDDR
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<Fallenou> like GDDR5 ?
<lekernel> yeah, it's 4.5Gbps/pin
<Fallenou> why don't they use "GDDR" for main memory then ? what's the drawback ?
<lekernel> it would be *great* to throw that into the M3 instead of a mess of multiple chips of DDR3
<lekernel> but with the shitty kintex-7 I/Os you can only go to 1.8Gbps/pin
<lekernel> and with lots of jitter
<lekernel> if you're using those PLLs
<Fallenou> and withVirtex 7 ? (isn't it faster ?)
<lekernel> seriously we're talking about 150ps of jitter here... that's 27% of your timing budget lost to that crappy PLL
<Fallenou> wow
<lekernel> I'm tempted by adding an external clock chip with a more reasonable (< 1ps) jitter level
<Fallenou> to have the correct frequency directly, with no PLL/DCM
<lekernel> problem is, in case of fuckups, PCB respins are expensive
<Fallenou> why would it be more expensive ?
<lekernel> virtex 7 is super expensive
<Fallenou> clock chip is harder to solder than current osc ?
<lekernel> well, because you're routing a lot of high speed, length matched traces between a clock chip, 8 DDR3 chips and a FPGA
<lekernel> if you have skew, it can be harder to correct
<Fallenou> ah yes you mean you have to modify the routing
<lekernel> though some clock chips have multiple outputs with configurable phase... need to look at that
<Fallenou> heh, like a DCM/PLL but on a chip
<Fallenou> this clock chip would replace the current osc and only be connected to the FPGA via a GCLK io ?
<Fallenou> no direct connection to DDR , right ?
<Fallenou> or direct connection, but skew adjustment for nets between FPGA and DDR chip ? in order to take into account the time for the clock to go through the FPGA ?
<lekernel> well, you'd need multiple phase aligned clocks, one for the 1.8Gbps data transfers and the other for the system (since you can't run it at 900MHz)
<lekernel> maybe you can get away without a direct DDR connection, yes
<lekernel> also, depending on how you deal with DQS, the PLL jitter might still be acceptable
<lekernel> anyway, I'm a lot more worried about marketing than DDR3 now
<Fallenou> yes that's what I understood
<Fallenou> is there something new about M3 ? marketing ideas ? technical ideas ?
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<wpwrak> lekernel: if you have to add a clock chip but can do it in a way that allows you not using it (either by FOGA configuration or just not soldering it), then you'd have less design risk
<wpwrak> also, if you market the critter for a specific purpose (e..g, video mixing), then technical specs don't matter all that much, as long as it does the job
<wpwrak> so DDR4 is not the enemy. 4K or DVI-du-jour may be, though.
<lekernel> you still need a lot of memory bandwidth ...
<lekernel> which GDDR5 would better provide if the FPGA I/O and PLL weren't so lousy
<Fallenou> wpwrak: (technical specs don't matter all that much, as long as it does the job) well yes that's something we learned through the Milkymist experience so far :)
<Fallenou> we don't care we are not 1 Ghz/DDR4, but we indeed would care to have 1080p and hdmi
<wpwrak> yeah. there are two really simple questions: "does it do what it promises to do ?" and "is what it does useful for me ?"
<Fallenou> sure
<Fallenou> and does it do as well (or better) as what I can have elsewhere ?
<wpwrak> of course, at some point, price enters the equation too
<Fallenou> yes
<wpwrak> competition is included in the 2nd question: if the competition already does this and does it better, then what it the M3 does isn't so useful for me
<wpwrak> s/it the/the
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