lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<wolfspraul> first milestone reached - xiangfu verified the fpgatools generated AND design in his slx9
<wolfspraul> now... next steps, let's see
<wolfspraul> first a truckload of hardcoded/left-aside things in the sources, all over the place
<wolfspraul> then the next design will be a counter
<wolfspraul> the counter adds a clock (dcm), and jtag/bscan
<wpwrak> you have a working AND ? congratulations !!
<wolfspraul> that's a whole different level from the AND gate, maybe a realistic goal for that counter is 1 month...
<wolfspraul> yeah well, many more steps needed, but ok
<wolfspraul> too much hardcoded stuff
<wpwrak> does the AND do I/O too ? or is it just internal ?
<wolfspraul> the 'design' has maybe 20-30 bits on, you could hardcode the whole thing ;-)
<wolfspraul> no no, xiangfu can control a led (the out-pin) with 2 in-pins
<wolfspraul> in an AND-way
<wpwrak> kewl
<wolfspraul> yes it's a good step, but also not more than that, too much is missing
<wolfspraul> need to continue in the autotester, wire model, features galore, everywhere
<wolfspraul> too many to list here really
<wolfspraul> but the next goal is easy to understand: a counter
<wolfspraul> 1 month
<wolfspraul> if that counter works, a lot more things need to be supported in the chip, compared to today
<wpwrak> now things move more quickly :)
<wolfspraul> the AND design is called hello_world and looks like this https://github.com/Wolfgang-Spraul/fpgatools/blob/master/hello_world.c
<wolfspraul> that will write the design to stdout as a floorplan, so you can run ./hello_world | ./fp2bit - hello_world.bit to create the configuration file
<wolfspraul> next: counter
<wpwrak> hmm, how about storing failure inside "rc" ? that way, you don't need error checking all over the place
<wolfspraul> how?
<wpwrak> and maybe have a "debug" mode where it drops out immediately when something goes wrong
<wolfspraul> 'storing failure'?
<wolfspraul> the apis are still in flux, in addition to have lots of unimplemented cases behind the scenes
<wpwrak> void fpga_whatever(... *model) { if (model->error) return; do_stuff(); if (trouble) { model->error = 1; return; } ... }
<wolfspraul> having
<wpwrak> or, better, make it "rc".
<wolfspraul> ouch that looks ugly to me, but ok :-)
<wolfspraul> you mean just let the model with 'stored error' pass through all sorts of functions on the way out?
<wolfspraul> is that common practice somewhere?
<wpwrak> then you can have an int fpga_error(... *model) { int tmp = model->rc; model->rc = 0; return tmp; }
<wpwrak> stdio has ferror for such things
<wpwrak> you can still return error codes if you want. but checking then becomes optional
<wolfspraul> then you have to check on the inside of every function call though
<wolfspraul> it's a nice idea, I just have never seen it like this
<wolfspraul> is this common practice somewhere?
<wpwrak> the most common practice is just to ignore errors ;-)
<wpwrak> and if you have such a large number of checks, that's what people will be inclined to do
<wolfspraul> there may be less functions later, these apis are in flux
<wolfspraul> you would hope there are less calls...
<wolfspraul> but sure the error handling can be in model->rc as you said
<wolfspraul> I would still return it but checking is optional
<wolfspraul> why not
<wpwrak> i mean, in theory, nothing should ever go wrong in your program. it's not like kernel APIs that fail quite regularly in non-catastrophic situations
<wolfspraul> just wondering about some precedent in other libs/codebases...
<wolfspraul> oh no, many things can go wrong
<wolfspraul> in routing or configuration attempts etc.
<wolfspraul> even more so latr
<wpwrak> sure. but that's bad requests.
<wpwrak> program errors. not just the universe conspiring against you
<wolfspraul> sure, but I need rock-solid error handling
<wpwrak> exactly :)
<wolfspraul> anyway, thanks for the model->rc idea
<wolfspraul> it means checking on every incoming call though
<wpwrak> you could have model->debug that then does an abort. maybe make a macro #define TROUBLE(_rc) do { if (!model->rc) model->rc = (_rc); if (!model->debug) return (_rc); fprintf(stderr, "rc %d\n", (_rc)); abort(); } while (0)
<wpwrak> that way, you'll know instantly if you tripped over something. and you only need more sophisication if you actually expect errors or if aborting is unacceptable (e.g., if it's some interactive editor or such). but i think it'll be a very long time until you need this level of sophistication, if ever :)
<wolfspraul> I'll think about the model->rc thing first
<wpwrak> (TROUBLE macro) if you check on entry, the if (!model->rc) test isn't even necessary. just set it and return
<wolfspraul> more important is to fill in many more missing pieces about the chip
<wpwrak> return/abort
<wolfspraul> because right now the AND thing is working, but it's far too many things that are hardcoded imho
<wpwrak> strict error checking just helps to avoid chasing ghosts :)
<wolfspraul> I need to make one step back and think about the right order of where and how to continue now, since there are just so many things
<wolfspraul> the counter will hopefully provide the needed focus, and then I fill in missing things left and right
<wolfspraul> that's the plan...
<wpwrak> sounds good
<wpwrak> so all those functions really need so many parameters ?
<wpwrak> e.g., couldn't fpga_find_iob just return a struct iob * instead of a set of variables ?
<wolfspraul> ah sure, this all could be changed in many ways
<wolfspraul> my general guideline is shorter and more readable code
<wolfspraul> which is at odds sometimes, but when in doubt I first go for 'shorter'
<wpwrak> yup, that's what i mean :)
<wpwrak> short calls, little redundancy
<wolfspraul> but shorter including all codes, I also write all the struct stuff on the other side...
<wpwrak> ;-)
<wolfspraul> there is no point for me to 'optimize' the api when I have only looked at 10% of cases or so
<wolfspraul> so I just add case by case, and cleanup carefully
<wolfspraul> because there will be more cases coming that require another round of cleanup/restructuring anyway
<wpwrak> yeah, you can clean up things as you go. or when you're bored or suffer a "writer's block" :)
<wolfspraul> I have this issue allover the codes, really
<wolfspraul> the thing stands at about 16k lines right now, I think
<wolfspraul> by the time I have a somewhat nice counter working, it's probably over 20k
<wolfspraul> so you look at those 70 lines hello_world, and complain about a few error checks and parameters :-)
<wolfspraul> which is all correct, and good feedback
<wolfspraul> but that hello_world is so unbelievably clean already! :-)
<wolfspraul> (compared to the messy 16,000 lines behind it...)
<wolfspraul> the one thing I will stay away from for sure is C++
<wolfspraul> which is tempting at times especially when creating new aggregate yet simple data types
<wolfspraul> but no, thanks
<wolfspraul> I stay clean :-)
<wpwrak> you'll always have "struct" :)
<wolfspraul> in C++ you can do nice things with constructors etc.
<wolfspraul> but no worries
<wolfspraul> I will not remove the error checks with exceptions :-)
<wpwrak> ;-)
<wolfspraul> throwing some stl templates?
<wolfspraul> so: counter now
<wpwrak> even those exist in C. longjmp :)
<wolfspraul> counter counter counter
<wolfspraul> yeah
<wpwrak> yeah, counter is better than templates ;-)
<wolfspraul> I vaguely remember using that many years ago
<wolfspraul> counter now, goal: 1 month
<wolfspraul> that's aggressive, but I try
<wolfspraul> maybe I make a little hello_world video this week, to relax
<wolfspraul> it's nice to walk throuhg the steps and see the led go on and off :-)
<wpwrak> oh yes, you should
<wpwrak> ;-)
<wpwrak> always remember the motto: "do good things and brag about it" :)
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<Fallenou> hello !p
<Fallenou> congratulations wolfspraul !!
<Fallenou> this is so amazing to see your fpga tool working :)
<wolfspraul> thanks, but keep it in perspective
<wolfspraul> it supports 0.00x% of what the chip can do
<wolfspraul> I changed my next step a little - not the counter right away but just a blinking led first :-)
<wolfspraul> that means only add a clock, not jtag/bscan
<wolfspraul> then the counter after that
<Fallenou> I don't fuckin care if it supports 0.000001% of the chip :p
<Fallenou> for now it does something with the chip
<Fallenou> a led blinks !
<Fallenou> that's more than enough for a lot of people ;)
<Fallenou> well for now it blinks manually, or maybe you can hook up an arduino to control fpga inputs :p
<Fallenou> let's make it blink automatically ;)
<wolfspraul> yes blinking_led (clock controlled) next
<wolfspraul> after the AND milestone I will take a one or two day break though :-)
<Fallenou> sure
<Fallenou> and make a youtube video !
<wolfspraul> Fallenou: what do you think we should get to work in the chip next?
<wolfspraul> I am thinking about a bit more debug instrumentation first, logic analyzer, serial/usb/spi, jtag of course, etc.
<Fallenou> when clock and dcm works , maybe add BlockRAM support ? :)
<wolfspraul> ah yes, of course
<Fallenou> then you can scan a blockram and SPI it out to a gpio as a testbench
<wolfspraul> bram and macc
<wolfspraul> but I was thinking more about real-life use cases
<wolfspraul> maybe too early now to even think about
<wolfspraul> more instrumentation first...
<Fallenou> well until you have "almost everything" working it's hard for real life use cases :)
<Fallenou> just do testbench like your led blinker
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<wpwrak> i concur: there's nothing new in "real life applications", so they can wait
<larsc> wolfspraul: yeay!
<larsc> :)
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<lekernel> wolfspraul: good job:
<lekernel> !
<Fallenou> lekernel: nice they seem to at least want to spend time on fixing segfaults on their tools
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<cde> wolfspraul: congrats :)
<cde> as somebody once said, "you'll be free, hackers. you'll be free"
<kristianpaul> cheers wolfspraul :) !
<wpwrak> I have a dream that one day the hackers will rise up and and cast away the manacles of closed FPGA tools. I have a dream today. And when this happens we will be able to join hands and sing: "Free at last ! Free at last !"
<Fallenou> can I quote you in a tweet ? :p
<kristianpaul> :-)
<wpwrak> ;-)
<wpwrak> it's too long for that. you'll need at least two tweets :)
<Fallenou> sure :p
<Fallenou> I think it's worth it
<wpwrak> let's fix some typos then, s/and and/and/
<wpwrak> and perhaps make it sound bettter with s/we will/we will all/
<Fallenou> let's keep the thuth of the spontaneous declaration :p
<Fallenou> hop, tweetd !
<Fallenou> +e
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<wpwrak> and there's an "all" in there that i missed on the first try :)
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<wpwrak> Fallenou: ah, but your tweets lack context. should link to the project's github page
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<Fallenou> wpwrak: I tweeted it a bit earlier in the day
<Fallenou> I think my followers will get the link :p
<wpwrak> ah :)
<wpwrak> so wolfgang should better prepare the press conference. well, it'll take the journalists of the world a while to fly over to beijing ...
<Fallenou> hehe sure
<Fallenou> it reminds me I must commit harder !
<mwalle> hi
<mwalle> missed many thinks i guess ;)
<mwalle> congrats wolfspraul
<mwalle> :)
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<Fallenou> hum
<Fallenou> if I map vaddr A to paddr A
<Fallenou> say DTLB is disabled for now
<Fallenou> I write the value B to (paddr) A
<Fallenou> oh, forget about it
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<mwalle> Fallenou: when does an itlb miss happen?
<mwalle> eg. calli N, where N is a non mapped address @0x1000
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<mwalle> and the instruction calli 0x1000 is at 0x200
<Fallenou> it happens when an instruction goes from address stage to fetch stage, with ITLB enabled
<Fallenou> and if ITLB misses
<Fallenou> ok let me check
<Fallenou> so the call will at some point make pc_a be 0x1000
<Fallenou> and when pc_a goes to pc_f, bim itlb miss, excepion etc
<Fallenou> +t
<mwalle> i guess calli is still executed
<mwalle> and the itlb miss happens at 0x1000, that is BADADDR is 0x1000
<mwalle> what is ea?
<Fallenou> yes calli is executed
<Fallenou> it's the fetch of 0x1000 which triggers the MISS, not the execution of calli
<Fallenou> yes BADADDR is 0x1000
<Fallenou> ea is the instruction being executed (pc_x) when 0x1000 was being fetched
<Fallenou> let me run a simulation with itlbtest :)
<Fallenou> EA is 0x1000
<Fallenou> EA == BADADDR in case of ITLB miss
<Fallenou> which seems correct, else it would not work
<Fallenou> we need to jump back to our call target upon eret
<Fallenou> does it make sens to you ?
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<mwalle> Fallenou: yes that makes sense ;)
<Fallenou> in some way it's kind of magic, I don't remember right now why it works
<Fallenou> because in theory EA gets the address of the instruction in X stage , not the one in F stage
<Fallenou> I think I must be delaying the exception or something after the miss is detected so that it happens when the cause of the miss is in X stage
<Fallenou> something like that
<Fallenou> it's sad that I don't know why it works :p
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<Fallenou> XilinxInc started following you <= ahah !
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<Fallenou> gn8 !
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<wpwrak> they're after you ! :)
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<mwalle> gn
<mwalle> gn8
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