lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<mwalle> wpwrak: well actually its more accurate ;)
<mwalle> wpwrak: but yes, there is still many things (including some legend)
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<mwalle> but feedback is welcome, eg what does confuse you? just that its different form the lattice one?
<wpwrak> most of all, what the signals mean/do. also, most of them are inputs without corresponding outputs.
<mwalle> wpwrak: btw do you actually sleep? :)
<mwalle> as i said, thats the dataflow, the controls are still missing, as is the bypass network, i guess they deserve an own sheet
<azonenberg> mwalle: lol if lm32's forwarding is as complex as the MIPS-based softcore i'm working with for my thesis it needs a page at least
<wpwrak> (sleep) yeah, i saw that you wrote some 3 minutes before my reply. i had just gotten up :)
<mwalle> azonenberg: imho there should be one sheet, which gives a rough overview, whats happening
<azonenberg> Actually, now that i look at things, my forwarding isn't as bad as i remember
<azonenberg> 116 lines including the BSD license header and comments and whitespace
<azonenberg> the actual logic doesn't even start until line 86, the rest is signal declarations and header comments
<azonenberg> fits in one screen
<wpwrak> all of the form a1=(a&b&c&d&e)||(f&g&h&i)... ? :)
<azonenberg> lol no :P
<azonenberg> that's the public version of the codebase which is a few months out of date, i'm now developing on a private branch and will merge back when i publish my thesis
<azonenberg> dont want to give away all of my secrets before the paper is ready :P
<azonenberg> but that file i dont think has changed much, if at all, since
<wpwrak> the code is too readable. someone could figure out what it does :)
<azonenberg> Lol
<azonenberg> The CPU is nothing particularly new
<azonenberg> i just couldnt find any open-source MIPS-1 implementations that were well documented so i had to make one
<wpwrak> ;-)
<azonenberg> but all of the NoC stuff etc is where my real research is at
<azonenberg> The CPU was a half-semester project just to kick things off
<wpwrak> "couldn't find any decent batteries. so i built me a fusion generator."
<azonenberg> Lol hey, it gets the job done
<azonenberg> it runs at 80 MHz in spartan6 without me even attempting to tune for performance, 5-stage pipeline, runs code compiled by unmodified mipsel-elf gcc, and is BSD licensed
<azonenberg> no MMU but it will be getting one shortly
<wpwrak> neat :)
<azonenberg> The only file in the project more than 1k lines
<azonenberg> i tried to keep it nice and modular
<azonenberg> but yeah, all of the fun work lately has been NoC and CPU-NoC integration
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<wpwrak> is "utica" an acronym or do you like tunesia ?
<mwalle> azonenberg: the bypassing/forwarding in lm32 is rather simple
<azonenberg> wpwrak: it's actually named after a nearby city
<azonenberg> as are all of the simple 8/16 bit cores i made to learn verilog
<Fallenou> Hi !
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<lekernel> hi wolfspraul & all
<Fallenou> morning
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<mwalle> wpwrak: still only data flow ;)
<Fallenou> hi mwalle I received your email, as soon as I have a few minutes I will do it :)
<Fallenou> do you doubt the simulation will ever run if I disable icache?
<Fallenou> if the simulation runs well, what do you want me to look at?
<mwalle> pc_* :)
<Fallenou> ok ! =)
<mwalle> esp. related to the clock, eg if there is a stall somewhere
<mwalle> ah and i_cyc_o
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<Fallenou> mwalle: looks nice ! much more precise than the previous one
* Fallenou disabled icache and mmu and tries to run simulation
<Fallenou> it's been a while since I last tried to run it without mmu :) so I have a few compilation errors =)
* Fallenou adds more ifdef
<Fallenou> ok it runs!
<Fallenou> code runs, uart works and it prints stuff =)
<Fallenou> so, looking at wires right now
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<Fallenou> here you go
<Fallenou> tell me if you miss some piece of informatio,n
<Fallenou> don't pay attention to wishbone latencies, they are random
<Fallenou> so it's normal if some wishbone transactions are faster than others
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<wpwrak> mwalle: looking better by the minute :)
<larsc> not bad
<mwalle> Fallenou: have a look why stall_x is asserted please
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<Fallenou> ok
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<mwalle> Fallenou: btw is there an vcd export? (maybe of a given range)
<mwalle> err, stall_m
<mwalle> ahh lol
<mwalle> Fallenou: nevermind :) i found the signal, i was looking for
<Fallenou> great !
<mwalle> CFG_SIZE_OVER_SPEED << what might this be
<mwalle> "over speed", aha ;)
<Fallenou> ahah
<Fallenou> it's not defined
<mwalle> yeah of course its not, the code is cluttered with such things
<Fallenou> hard to read, a lot of "generate" and "ifdef"
<mwalle> bbl, supper
<Fallenou> good apetite !
<mwalle> but you get used to it ;)
<mwalle> thanks
<Fallenou> unfortunately there is no VCD export button in the GUI
<Fallenou> but I think you can generate a VCD using the ISim shell prompt
<Fallenou> I've never done it though
<GitHub194> [milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Zry4Vw
<GitHub194> [milkymist-mmu-simulation/master] Fix compilation with MMU disabled - Yann Sionneau
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<GitHub32> [milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Kt6yxQ
<GitHub32> [milkymist-mmu-simulation/master] Fix typo - Yann Sionneau
<GitHub72> [milkymist-mmu-simulation] fallen pushed 1 new commit to master: http://git.io/Lhn4mQ
<GitHub72> [milkymist-mmu-simulation/master] Make simulation silent when verbose mode is not activated - Yann Sionneau
<GitHub104> [milkymist-mmu-simulation] fallen pushed 2 new commits to master: http://git.io/XXMIwg
<GitHub104> [milkymist-mmu-simulation/master] Add support for "Draw Me a Pipeline" tool in CPU simulation - Yann Sionneau
<GitHub104> [milkymist-mmu-simulation/master] Removes a few display forgotten in previous commit - Yann Sionneau
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<mwalle> ah cool, at least without i cache enabled, the simulation seems to work with iverilog
<Fallenou> oh :)
<Fallenou> very nice !
<mwalle> Fallenou: do you remember if you added some initializations in the icache/instruction unit?
<mwalle> 375 if (rst_i == `TRUE)
<mwalle> 376 begin
<mwalle> 377 state <= `LM32_IC_STATE_FLUSH_INIT;
<mwalle> 378 flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
<mwalle> 379 refill_address <= {`LM32_PC_WIDTH{1'bx}};
<mwalle> 380 restart_request <= `FALSE;
<mwalle> 381 end
<mwalle> refill_address is strange, i saw you changed that to 1'b0
<mwalle> lekernel: does this even make sense?
<mwalle> to say set this value to dont care on reset? :)
<Fallenou> to me it is a bug, at least for simulation
<Fallenou> in FPGA it's not a problem I guess
<Fallenou> cause x must mean 0 or 1
<Fallenou> but in simulation it's a problem to have a "x" value, it will make all logical operation fail :/
<mwalle> yeah but why do i reset a register to 'dont care'?
<larsc> mwalle: it's not dont care, it's unkown
<Fallenou> well IMO you should not
<larsc> for case 'x' is don't care, for assignments it is unkown
<mwalle> larsc: sure? read it as, i dont care for this bit, let the synthesizer figure out the best value for it?
* Fallenou would say like larsc but not sure
<mwalle> anyways, if its unknown or don't care, why should i use that in a reset?
<larsc> it makes sense for simulation
<Fallenou> larsc: well it makes sens but it also makes everything fail
<larsc> Fallenou: could be a bug somewhere ;)
<Fallenou> because AFAIK 0 and x == x instead of 0
<Fallenou> and 1 or x == x
<larsc> Fallenou: yes, x will propagate
<larsc> that's the point of it
<mwalle> mhh.. but 1 or 'unknown' is 1
<Fallenou> so if the cache contains 'x' you're basically screwed, it will propagate almost everywhere
<larsc> I think the intend is that the value should not be used before it has been properly initialized
<Fallenou> so we should add a few tests for x values in a few places
<Fallenou> there is basically no test for x value in lm32 code afaik
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<larsc> you should not have to test for x
<mwalle> 1 || x == 1
<mwalle> 0 && x == 0
<Fallenou> really?
<mwalle> yeah
<Fallenou> OK I smoked something bad then
<Fallenou> sorry for the misinformation :)
<larsc> 0 | x = x and 1 & x = x
<mwalle> yeah, because then x matters :)
<mwalle> i can only imagine that the refill_address is initialized just for completness
<Fallenou> oh yes sure, I wasn't paying attention to operand order
<mwalle> if you omit this line, the simulation is still uses 'unknown' (yeah in this sentence dont care makes no sense ;) and the hardware has either 0 or 1
<larsc> Fallenou: which memory gets initialized to all x? way_0_tag_ram?
<Fallenou> I don't remember what was wrong I fixed it when I started the project with simulations
<mwalle> mh my icache toggles between CHECK and REFILL
<Fallenou> check register file values, if they are not xxx
<Fallenou> check r0 value, do you put 0 in it ?
<mwalle> Fallenou: yeah r0 is zero
<Fallenou> going to sleep, I hope tomorrow or the day after I will be able to push "draw me a pipeline" ;)
<mwalle> Fallenou: could you do me one quick favor? :)
<Fallenou> it depends, ask !
<mwalle> initial $display("XXX %d %d", addr_offset_width, addr_offset_msb) << put this in lm32_icache.v and check the output
<Fallenou> sorry i really gotta go !
<Fallenou> will do it tomorrow :x
<Fallenou> gn8
<mwalle> ok, np, gn8
<larsc> shouldn't those be const?
<mwalle> larsc: yeah, but i changed the clogb2 to the builtin $clog2
<mwalle> but i'm already on another track to follow
<larsc> what do you get, 'XXX 1 2'?
<mwalle> yeah
<mwalle> seem right i know ;)
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<mwalle> going to bed, too
<mwalle> gn8
<mwalle> larsc: (clog2) i see only two wb accesses, that would be 8 bytes, but bytes_per_line is 16
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