lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<GitHub136> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/fecab5518bfef72105ab4ba437f0cad51fc4e6f4
<GitHub136> [migen/master] transform/unroll_sync: support generator function - Sebastien Bourdeauducq
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<GitHub28> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/daee4fb58c94db71885bfacbded5e4b77f8f6a93
<GitHub28> [migen/master] transform/unroll_sync: autodetect in/out - Sebastien Bourdeauducq
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<Fallenou> why using only 1 exception handler for both i/d tlb misses is good ?
<Fallenou> instead of 1 handler for each
<Fallenou> because it might not be so simple to make this change
<Fallenou> It's quite easy to keep 2 exception vectors, each calling the same C function which would then be the "unique" tlb miss exception handler
<Fallenou> but having only 1 exception vector is not so easy
<Fallenou> I don't know if there is a big performance problem with keeping 2 exception vectors (the 8 instructions in crt0.S)
<larsc> why is it complicated to make the change?
<Fallenou> for now I see only one problem but I don't have easy solution to solve it
<Fallenou> in dtlb_miss_handler I need to do a addi ea, ea, -4
<Fallenou> before saving the registers and calling the dtlb_miss_handler
<Fallenou> but since .save_all routine saves all the registers afterward, I won't be able to make this change (ea -= 4) after save_all is called
<Fallenou> because it won't do anything
<Fallenou> at the end of the exception_handler there is the .restore_all_and_eret routine which restores all registers (and would then overwrite my ea) and then do "eret"
<Fallenou> eret does jump to "EA"
* Fallenou is not sure if he is clear enough
<larsc> I understand it
<Fallenou> or maybe I need to add detection of TLB miss source in "save_all" routine, to make it do the job on EA before saving it
<larsc> or in restore_all
<Fallenou> yes
<Fallenou> just before the eret call
<Fallenou> would be a better idea indeed
<Fallenou> so my question would be, what's best : doing this hack (a check on tlb miss origin in .restore_all_and_eret)? or keeping 2 exception vectors (calling the same C function)?
<larsc> hard to say
<Fallenou> I don't quite remember in the first place why we wanted to only have 1 exception (vector? or handler?) for misses (and another one for permission faults)
<larsc> me neither
<Fallenou> I guess it's good for cache
<larsc> I think mwalle was pushing for it
<Fallenou> or maybe wpwrak or both
<Fallenou> let's ask them :)
* Fallenou ping ping
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<GitHub37> [migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/daee4fb58c94...31cdb02eff9b
<GitHub37> [migen/master] bank/description: regprefix - Sebastien Bourdeauducq
<GitHub37> [migen/master] actorlib/spi: typo - Sebastien Bourdeauducq
<wpwrak> as far as a i remember, i didn't favour any of the two choices. if separate vectors are more convenient, then i don't see a need for trying to have just one
<Fallenou> but then we need to have exception vector as well for permission faults
<Fallenou> can ITLB issue permission fault ?
<Fallenou> dtlb can issue permission fault for read/writes ...
<Fallenou> ITLB ... I don't see what permission fault it can generate ... either the page is mapped (and then we can say it's executable) or either it is not mapped (and it's a miss)
<Fallenou> right ?
<Fallenou> or I am missing something ?
<Fallenou> am I*
<Fallenou> so can we say permission fault is just about DTLB ? (and then i's easy for this problem)
<Fallenou> it's*
<wpwrak> i think itlb and dtlb should have the same page tables. otherwise you get a lot of duplicate work. so "not mapped" to indicate "not executable" would require that the software does the checking, increasing the execution path of the handler
<Fallenou> oh, the same page tables ???
<Fallenou> hum I think lekernel was thinking about the contrary
<Fallenou> this kind of decision is a big change in the code of the mmu
<Fallenou> so this deserves an email to the mailing list :)
<Fallenou> so that anyone can give his opinion
<Fallenou> so that I don't change everything for nothing :p
<wpwrak> ;-)
<Fallenou> for now each TLB has it's own "blockram" page table
<Fallenou> which simplifies as you said the case of itlb miss which indicated the page is not mapped and then not executable
<Fallenou> well no, not exactly
<Fallenou> itlb miss just indicates it's not in the "tlb" , it could be mapped, that would need a check in linux internal structures
<Fallenou> to check if there is a mapping
<wpwrak> wait .. the tlb shouldn't really know about page tables. the mapping page table -> tlb is done in the handler.
<Fallenou> yes sure
<Fallenou> I just mixed up things :)
<Fallenou> oh ok you were talking about the page table ...
<Fallenou> right
<wpwrak> :)
<Fallenou> indeed the same page table
* Fallenou must be tired ...
<Fallenou> and in the page table you have the permission rwx, if the permission x is present and itlb misses, then we update the itlb line with the correct mapping
* Fallenou needs to think about this a little bit more
<Fallenou> I will shoot an email soon about that :)
<Fallenou> need to go, thanks !
<wpwrak> np ;)
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