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<azonenberg>
wolfspra1l: So I heard back from my FAE
<azonenberg>
the Artix-7s on digikey now are first-round engineering samples and are CSG324 and FGG676 only, in -1 and -2 speed grades only
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<azonenberg>
Second round samples will include FGG484 (I think probably the whole range of packages) and be -1 and -2 only
<azonenberg>
those are expected to be out some time next month
<azonenberg>
then early Q1 2013 volume production starts
<wolfspra1l>
azonenberg: nice
<wolfspra1l>
how about ftg256?
<azonenberg>
wolfspra1l: i didnt ask but it was implied that the second round samples will include all package combos
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<wolfspra1l>
ok
<wolfspra1l>
well I have really a lot of good features in the slx9 to work on anyway
<wolfspra1l>
currently back in the logic blocks and luts
<azonenberg>
:)
<wolfspra1l>
this time I'm going to add much more including all slice types (m/l/x), o6/o5 lut pairs, carry chain, latches, etc. etc.
<azonenberg>
:)
<azonenberg>
one thing is for sure, all of the work i am doing for my research is resulting in me getting really good at mental logic synthesis
<wolfspra1l>
after this round the only thing missing will be ram/rom and shift-registers
<wolfspra1l>
I will put that aside until the next round
<azonenberg>
as in, i can give pretty much exact netlist and resource estimates for a module given just a pencil and paper
<wolfspra1l>
can't exhaust myself in one tiny thing, have to go back to clocks, bufg, jtag, and an infinite list of other missing things :-)
<azonenberg>
and even synthesize to primitives given enough time
<wolfspra1l>
good
<wolfspra1l>
since primitives are the only thing you can feed to fpgatools anyway :-)
<azonenberg>
lol
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<larsc>
azonenberg: next time I need a bitstream I'll just come to you ;)
<azonenberg>
larsc: If you want bitstreams talk to wolfspra1l :P
<azonenberg>
my brain only goes to netlist level
<azonenberg>
well ok, i can map and PAR to some extent too
<larsc>
but once you have the netlist you can use wolfspra1l tools
<azonenberg>
His tools want a fully placed and routed netlist atm
<azonenberg>
so i'd have to map and par manually too
<wolfspra1l>
yes :-)
<azonenberg>
Not that i cant do it, but its a little bit of a pain to do
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<azonenberg>
on the other hand, mental synthesis i find is a very good way to santiy check how big some module is going to be
<azonenberg>
and how long the critical path is
<azonenberg>
Dont worry about details like exactly what the logic function implemented by some LUT is
<azonenberg>
I just think about what decisions need to be made with what data
<azonenberg>
dataflow level, pretty much, as well as storage requirements
<azonenberg>
and i usually end up with a slice-by-slice model for what the thing is going to look like before i write a single line of RTL
<azonenberg>
then i just write the code and the synthesis tool usually generates pretty much exactly what i expect
<azonenberg>
A lot of times i just write RTL without thinking much about what goes on under the hood but if i have any doubts as to how things are going to work i find this is a good way to sanity check
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