<Fallenou>
wow they waited for 14.1 to fix such a thing ...
<Fallenou>
amazing
<mwalle>
but that still doesnt fix my problem ;)
<mwalle>
i already removed the the -1 from all clog2 calls
<Fallenou>
ah ok I was not understanding why you still have the "-1" in your commit
<Fallenou>
so now you got rid of it
<Fallenou>
so now you should have addr_offset_width == 2 , right ?
<mwalle>
probably, tried it yesterday, cant remember ;)
<mwalle>
Fallenou: could you send me a vcd (isim parameter -vcdfile out.vcd) from the first few cycles, where the icache is filling and some later instructions loads hit the cache?
<mwalle>
Quartus II 9.1 supports the built-in $clog2 function from Verilog 2005
<mwalle>
so altera should be fine too
<mwalle>
and nobody uses lattice *fg*
<mwalle>
mh does lattice even have an own synthesizer?
<mwalle>
or do they always use synplify?
<lekernel>
mwalle: don't use 'x', it only allows for minor synthesis optimizations and can easily waste your time with weird bugs and/or simulation/synthesis mismatches
<mwalle>
lekernel: that was found in the lm32 source ;)
<mwalle>
and i wondered what the reason could be to assign 'x' to a register when it is reset
<lekernel>
what it means for the synthesizer is it will reset that register to the value/equation that causes the least logic to be used
<lekernel>
since S6 flip-flops have a dedicated reset pin, I guess this disables reset completely
<mwalle>
lekernel: and if i dont reset that at all?, eg omit the line in the reset case?
<lekernel>
that's fine if you don't have any code that depends on the reset value (and you probably don't, since it works with 'x')
<Fallenou>
mwalle: will try to send you the VCD this afternoon
<mwalle>
mh so i still have no reason why lattice put that into the source code :|
<mwalle>
s/reason/explanantion/
<lekernel>
maybe a coding style rule such as: "all registers should have a reset section"
<Fallenou>
well it works for me using ISim
<lekernel>
oh and
<Fallenou>
ah you mean the 'x', yeah I don't know
<mwalle>
lekernel: yeah that would also be my guess
<lekernel>
isn't there a risk that latches be generated when LM32 is configured for asynchronous reset and that line is not present?
<lekernel>
hmm, no, I guess that works. so it's probably just coding style.
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<mwalle>
mh, sensitivity on posedge rst, is a noop, so should be the same like there is just 'posedge clk' as sensitivity list, shouldnt it?
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<lekernel>
yes
<mwalle>
bbl
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* Fallenou
just had lunch with Alarm
<Fallenou>
he's a teacher in a French electronic high school
<Fallenou>
he would like to set up a workshop for his students using the M1 :)
<Fallenou>
that's pretty cool
<Fallenou>
he already has two complete Milkymist One box (with DMX spot, camera etc)
<larsc>
I was first confused a bit, because I though you had a firealarm during lunch ;)
<Fallenou>
ahah
<larsc>
but, yea I should have noted the capital A
<lekernel>
hey, is there anyone for whom http://ehsm.net/ doesn't work?
<lekernel>
(the website)
<xian9fu>
works fine here. 'exceptionally hard and soft meeting *2012 December 28-30 Berlin'
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<Grievre>
Is navre abandoned?
<lekernel>
it serves it purpose, which is to control the M1 USB ports (and not be a friendly full avr softcore)
<lekernel>
its purpose
<lekernel>
it's not abandoned, if you send a patch to the list i'll review it
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<Fallenou>
the website works fine for me lekernel (ehsm)
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<Grievre>
lekernel: also the opencores svn browse goes nowhere useful. This isn't your fault/responsibility but I was wondering if the solution was well-known
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<larsc>
lekernel: A few days ago ehsm.net did not work, now it works fine though
<lekernel>
Grievre: all milkymist source is on github, not OC
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<Grievre>
lekernel: oh, where's the navre code hiding?