sh4rm4 has quit [Remote host closed the connection]
sh4rm4 has joined #milkymist
Gurty has quit [Ping timeout: 244 seconds]
bkero` has joined #milkymist
bkero has quit [Quit: WeeChat 0.3.7]
bkero` is now known as bkero
bkero has quit [Changing host]
bkero has joined #milkymist
bkero has quit [Excess Flood]
bkero has joined #milkymist
bkero has quit [Changing host]
bkero has joined #milkymist
cladamw has joined #milkymist
kristianpaul has joined #milkymist
kristianpaul has joined #milkymist
kristianpaul has quit [Changing host]
xiangfu has quit [Quit: Leaving]
cladamw has quit [Quit: Ex-Chat]
Gurty has joined #milkymist
mumptai has joined #milkymist
Hawk777 has quit [Ping timeout: 255 seconds]
mumptai has quit [Ping timeout: 246 seconds]
mumptai has joined #milkymist
Martoni has quit [Quit: ChatZilla 0.9.89 [Firefox 16.0.1/20121011002034]]
Hawk777 has joined #milkymist
* Fallenou
ping mwalle
* mwalle
pong Fallenou
<mwalle>
seem you have a slow connection :b
<mwalle>
4 min rtt
<Fallenou>
I have 100 mbps fiber optic :(
<Fallenou>
really damn slow!
hypermodern has joined #milkymist
<mwalle>
in france, there is fiber to the home?
<Fallenou>
yes in big cities
<Fallenou>
a few ISP do provide FTTB or FTTH
<mwalle>
mom brb
* Fallenou
is asking on kernelnewbies channel if there is a linux kernel feature requiring write-only pages to be implemented in the MMU
<Fallenou>
if not, then indeed we just implement read-only, and a "permission fault" automatically means a write fault
<Fallenou>
which is much easier to implement
<Fallenou>
and then we don't care to fetch the faulty instruction
<Fallenou>
and indeed I think wpwrak is right, having the virtual address of the faulty instruction does not allow us to fetch the faulty instruction ^^
hypermodern has left #milkymist [#milkymist]
<larsc>
Fallenou: linux has no write only
<larsc>
writable always implies readable
<Fallenou>
ok thanks!
<Fallenou>
so that is sorted out :)
<Fallenou>
we don't need write-only, and therefore we don't need to check for the instruction generating the exception
<Fallenou>
much simpler :)
<Hawk777>
Fallenou, x86 and amd64 can't even do write-only pages
<Fallenou>
ok let say we don't want to out perform x86 for now ;)
<wpwrak>
100 mbps .. that's less than one byte per second. slow indeed. good that things are simpler now :)
<Fallenou>
:)
<Fallenou>
maybe I should have said 100 Mbps :p
<wpwrak>
aah ! now that's quite different. a thousand million times faster :)
elldekaa has quit [Remote host closed the connection]
<Fallenou>
I think itlb miss should generate an exception the same way the "Instruction Bus error" exception is generated
<Fallenou>
I should have a look on this one
<Fallenou>
to see how they deal with it (delay until X stage ?)
<Fallenou>
for data bus exception, the exception is raised right away, no delay
<Fallenou>
hum indeed they delay the exception until X stage
<Fallenou>
they use a register to pass the "error" information through the pipeline
<Fallenou>
decoding stage has a "bus_error_d" wire, which is passed to bus_error_x register at next pipeline cycle
<Fallenou>
and exception is only raised when bus_error_x is TRUE
<Fallenou>
(and valid_x is true as well)
<Fallenou>
My "itlb miss" information comes earlier though, at Fetch stage, but I guess I can use the same trick to propagate the information through the pipeline
<Fallenou>
I just have one more propagation cycle
proppy has quit [Quit: Connection closed for inactivity]
elldekaa has joined #milkymist
<larsc>
wpwrak: on my companies website all the product pages have all caps titles. We do offer 3MW ADCs ;)
<Fallenou>
ahah
<Hawk777>
You need to sell 3 MW DACs. For driving speakers :)
<larsc>
it acutally was a LOW POWER 3MV ADC ;)
<Fallenou>
interesting technology!
<Fallenou>
mwalle: talk to you later, going to sleep here, a bit tired!
<Fallenou>
I updated piratepad with new informations (about delaying exception and write-only not being needed) : http://piratepad.net/RSE6AWxIIa
<Fallenou>
gn8!
<wpwrak>
larsc: well, everyone if moving from analog to digital. so why not do it with power, too ? :)
<mwalle>
lol wpwrak :b
<mwalle>
there might be some problems with exceptions in the m stage
<mwalle>
the manual says data bus erros are imprecise
<mwalle>
data bus errors are raised in the m stage
<mwalle>
actually its the only exception raised in the m stage
<mwalle>
so if the m stage is the reason why the exception are imprecise, we'll have a problem