23:21 <mwalle> Fallenou: i guess we could stall the pipe if the dtlb is enabled and a load or store is to be executed

23:22 <mwalle> so we can decide in the X stage if theres a miss or not

23:22 <mwalle> of course this introduces a one clock cycle penalty for every load and store

23:25 <mwalle> otoh we could speculate that there is no miss, and in the case of a miss kill all instructions and restart at the exception vector (assuming it is easily possible to write EA this way)

23:32 <mwalle> i think we should start with the first