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<lekernel>
second option is best, CPU is slow enough already
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* Fallenou
does not like the idea of losing cycles
<Fallenou>
sorry if I don't answer quickly on proposals I have tons of things to do these days :/
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<mwalle>
lekernel: yeah and its the hardest to implement ;)
<mwalle>
therefore i'll give the first method a try, first
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<Fallenou>
mwalle: are you sure the way it's implemented right now (+ a few fixes maybe) is really not the good way of doing it ?
<mwalle>
Fallenou: almost sure, it is possible that the exception in m is not raised
<mwalle>
that is if the pipe from X back is stalled
<mwalle>
(eg an interrupt)
<Fallenou>
hum I'm pretty sure I will raise an exception if there is a dtlb miss in M stage
<Fallenou>
Since I keep exception_x asserted until I am certain exception_m will be assterted as well
<mwalle>
yeah but not the instruction in M will raise it
<mwalle>
but the one in X
<Fallenou>
the question is, will the exception be raised at the correct time
<mwalle>
and since has already reached M, it may be possible, that it passes through the pipe, although there was a miss
<Fallenou>
you mean, the instruction causing the dtlb miss will then be in W stage ?
<mwalle>
no in M
<mwalle>
but exceptions happen in X
<Fallenou>
yes
<mwalle>
so if stall_x is TRUE when the load which misses, is in M, no exception occurs
<mwalle>
but the load/store is executed because only A/F/D/X are stalled
<mwalle>
moving the exception handling to the M stage isnt possible, because an exception is treated like a branch, which is already resolved in X
<Fallenou>
23:45 < mwalle> so if stall_x is TRUE when the load which misses, is in M, no exception occurs < but it will happen some timer later
<mwalle>
Fallenou: but the load/store is already executed
* Fallenou
checking the code
<mwalle>
that is, there was a miss, but the store writes to memory anyway
<mwalle>
the whole data bus error is a messed hack
<mwalle>
basically you could just shutdown and enable a red light in case of a data bus error :)
<Fallenou>
nothing will be written in the dcache
<mwalle>
D_ERR_I not data bus error
<Fallenou>
because way_match will be false
<Fallenou>
and then the write enable will be false as well
* Fallenou
checking if something could be written back directly to main memory
<mwalle>
which write enable?
<mwalle>
dcache could possibly be disabled and cache is write through
<Fallenou>
way_dmem_we
<Fallenou>
in depends on way_match being true
<Fallenou>
and way_match depends on dtlb not missing
<Fallenou>
but yes I don't prevent the write through from writting to main memory
<Fallenou>
that's a problem
<Fallenou>
going to sleep, sorry I don't have that much time for mmu stuff these days :(
<mwalle>
mh either i have not the up2date code, or accidentally removed that
<mwalle>
but nonetheless i dont think we should go down that road and pass back the exception from M to X, eg. pretend the instruction in X causing the exception