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<azonenberg>
Anybody here work with the BSCAN primitive?
<mumptai>
the nor flash programmer of urjtag does, iirc
<mumptai>
(got to run) bye
<azonenberg>
i'm trying to make an API that allows point-to-point contact through multiplexers from one (or more) PC-based applications to cores on the FPGA
<azonenberg>
so that i can have say a gdb bridge and a bus sniffer both running simultaneously using the single jtag interface
<azonenberg>
via a packet-switched protocol using USER1 as an address, USER2 as the per-core IR, and USER3 as the per-core DR
<azonenberg>
so you basically have virtualized TAPs on each core
<azonenberg>
does the system i mentioned sound useful?
<azonenberg>
i want a TCP server that allows you to configure FPGAs with bitstreams, do boundary scan operations, and communicate with virtualized TAPs on fpgas through the USER* instructions
<azonenberg>
it's going to be nice and generic, i'm going to support the Digilent API, openocd, and possibly raw ftdi adapters as back ends
<lekernel>
can you make it generic enough that GDB isn't an assumption anymore?
<azonenberg>
Yes
<lekernel>
i'd use something like that to measure memory bandwidth, dataflow token rates, etc.
<azonenberg>
The goal is to expose an API that allows you to open a TCP socket to the server and then select "/scanchain0/device0/core2"
<azonenberg>
you will then use a simple frame-based format consisting of {opcode, length, data} or similar
<azonenberg>
for example "set IR to 16 bits 0xDEAD"
<azonenberg>
"set IR to 32 bits BAADC0DE and return result"
<azonenberg>
the idea is to use jtag as a link-layer protocol and define a socket-style transport layer on top
<azonenberg>
and then you can run any application-layer traffic you want on top of those connections
<lekernel>
also to control embedded logic analyzers
<azonenberg>
Yep
<azonenberg>
I intend to add a RED TIN module for it
<azonenberg>
It will also allow you to speak directly to the chip rather than to cores on it
<azonenberg>
to query serial numbers, do boundary scan, and Xilinx-specific commands for loading bitstreams etc
<azonenberg>
though you could of course add another class that derives from FPGA and JtagDevice other than XilinxSpartan6Device
<azonenberg>
It will support plug-and-play to the extent possible
<azonenberg>
automatically identifying FPGAs via IDCODE and then querying USER* instructions to see if one of my cores is present on it
<azonenberg>
and if so, finding out how many cores are present and getting ID codes off each
<azonenberg>
so you'll be able to autodiscover "JTAG plug-and-play controller at address 0", "LM32 GDB interface at address 1", "RED TIN logic analyzer at address 2"
<azonenberg>
So then you'd be able to start up RED tin and connect to the server and it'd give you a drop-down list of LA servers discovered
<azonenberg>
you could thus have multiple LAs present
<azonenberg>
i dont think chipscope can do that :D
<azonenberg>
the big problem with chipscope though is that it doesnt play well with softcore ICD since i think it monopolizes the USER* instructions
<azonenberg>
this system would be built around multiplexing and sharing from the start
<azonenberg>
And by virtue of being socket based, remote config/debug comes almost for free
<lekernel>
and it's horrible java bloatware
<azonenberg>
Lol
<azonenberg>
RED TIn is still a bit buggy but is getting there, and is like 2000 lines of C++ and verilog :D
<azonenberg>
1k of each roughly
<azonenberg>
lightweight, does exactly what it needs to and not a single thing more
<lekernel>
with more bugs than a rainforest. maybe it improved since then, but I never touched it again since I tried it in 2008, couldn't get it to work, and kept myself at a safe distance
<azonenberg>
Lol
<azonenberg>
while meanwhile RED TIN is open source and, while not fully debugged, the first beta tester i gave it to caught a memory controller bug within like an hour or two of downloading it
<azonenberg>
i'm a big fan of minimalism in hardware/software design
<lekernel>
I'll want to improve in-system debugging support in migen at some point
<azonenberg>
well feel free to use this system
<azonenberg>
I've only been working on it for a day or so (~1kloc) but will be pushing it to google code under a BSD license in a week or so once i have something actually usable
<azonenberg>
it's already able to connect to my Atlys via the embedded Digilent programmer, probe the chain, and identify the chip as an XC6SLX45 rev 3
<lekernel>
have a lib of cores ready that can capture bus transactions, analyze memory bandwidth usage and memory latency, or even replace complete cores with software simulations running on the computer
<lekernel>
this sort of things
<azonenberg>
Nice
<azonenberg>
I want to play with that at some point too
<lekernel>
all doable with a < 5 lines of code diff to your system
<azonenberg>
Make a bridge over jtag that connects my NoC to the PC
<azonenberg>
so i can have emulated and softcore nodes speaking freely
<lekernel>
it can work really nice with those "pytholite" compiled actors. when debugging you can run the suspicious actor on the computer and use print() etc. - then you just put it back into hw when you have fixed the bugs
<azonenberg>
Hmm, good idea
<azonenberg>
i need to play with verilog simulation more and see how to get it to bridge with native APIs
<azonenberg>
like, have a verilog module i instantiate in my simulation that bridges to C++ code or (indirectly) a hardware device
<azonenberg>
this could massively speed up verification
<azonenberg>
i should have done this a long time ago
<azonenberg>
writing C++ code to send stimuli to a module being exercised in hardware
<azonenberg>
whle having an internal LA capture bus traffic that module generates
<lekernel>
well the problem of doing it at the verilog level is you need to pause the FPGA basically at every cycle
<azonenberg>
No, you misunderstand
<azonenberg>
The integration would be done at the protocol level
<azonenberg>
my NoC is based on a packet-switched fabric
<azonenberg>
so packets would be generated by the simulator or PC code, when fully transmitted they'd be sent over jtag to the DUT, then sent at full speed onto the wire
<lekernel>
ah, yeah, so that's basically the same idea
<azonenberg>
i'm debating whether to make the jtag mux use the NoC too
<azonenberg>
because that would be cleaner but restrict usage somewhat
<azonenberg>
i might make two endpoints
<azonenberg>
have 16-bit addresses and you could have either a native front-end or a NoC front end
<lekernel>
"allow nerd deployments to be customized to customer needs"
<lekernel>
this almost sounds like something from dilbert :)
<azonenberg>
lol
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<azonenberg>
lekernel: so i have my jtag software speaking to the fpga now via USER1
<azonenberg>
the first design decision i have to make is the semantics of the interface
<azonenberg>
should i keep it JTAG-style with an IR and a DR for each peripheral?
<azonenberg>
i'm thinking maybe it'd be better to build it around packet switching
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<wpwrak>
do any modern-day datasheets actually use deg F ? :)
<azonenberg>
wpwrak: probably not, but i wasnt in the mood to convert
<azonenberg>
did you get a laugh out of it otherwise? :P
<wpwrak>
and i kinda doubt that you can provide fully functional nerd units with only 9 months lead time :)
<azonenberg>
and no, they ship with blank disks
<azonenberg>
you need years of firmware updates and configuration before they're usable
<azonenberg>
someone needs to port dd to nerdOS...
<azonenberg>
then you can just drop in a new firmware image
<wpwrak>
you could mention that the traditional bulk import of unscreened units has been suspended for the time being
<wpwrak>
a dfu-capable brain would actually be quite useful :)
<azonenberg>
lol
<larsc>
until you brick it
<wpwrak>
hmm, and wouldn't 100% oxygen be potentially damaging ? fwiw, you may also include atmospheric pressure and humidity. plenty of environmental factors to consider :)
<wpwrak>
ah, it's in the small letters ;-)
<azonenberg>
and yes, i am going to add a lot more stuff
<wpwrak>
larsc: i suppose you'd just unbrick it via dfu, no ? :)
<wpwrak>
just install the latest backup
* azonenberg
plugs jtag cable into wpwrak's brain
<wpwrak>
ouch !
<azonenberg>
wpwrak: you cant feel it
<azonenberg>
first off, boundary scan doesnt affect normal device functioning
<azonenberg>
so until i start loading new memories into your brain or moving your fingers you wont notice anything out of the ordinary
<azonenberg>
second, the brain does not have any sensory nerve endings in it :p
<larsc>
yea, quite funny, once you removed the skull you can keep poking the brain without people noticing it ;)
<larsc>
wpwrak: that won't work if you bricked your own brain
<wpwrak>
azonenberg: it's more the obstacles on the way to the brain that i suspect would give me a bit of a headache
<azonenberg>
details, details :P
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<wpwrak>
larsc: hmm, you have a point there. better have some one around to initiate the recovery
<azonenberg>
wpwrak: with any luck the TAP will still be functional
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