lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs :: EHSM Berlin Dec 28-30 http://ehsm.eu :: latest video http://www.youtube.com/playlist?list=PL181AAD8063FCC9DC
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<Fallenou> mwalle: indeed the address of the instruction changes how it behaves because the cache refill is not at the same moment
<Fallenou> ah nice (resizing icache line to 1024 bytes) :)
<Fallenou> you should get rid of any side effect like that
<Fallenou> what I did for my tests was to put 0/1/2/3 nops before my instruction sequence
<Fallenou> to move the cache refill at different places
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<GitHub153> [migen] sbourdeauducq pushed 5 new commits to master: https://github.com/milkymist/migen/compare/89643bc4346d...20d87682adf1
<GitHub153> migen/master 51e2e6e Sebastien Bourdeauducq: fhdl/verilog: remove empty cases
<GitHub153> migen/master 0b24a2f Sebastien Bourdeauducq: pytholite/io: support Wishbone writes
<GitHub153> migen/master f098c5c Sebastien Bourdeauducq: pytholite/compiler: pass keyword arguments to gen_io
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<GitHub30> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/0b7dd7bdce9606c90c78f8791e5d0fb051b560cb
<GitHub30> migen/master 0b7dd7b Sebastien Bourdeauducq: pytholite/io: fix Wishbone writes + support sel attribute
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<GitHub72> [migen] sbourdeauducq pushed 5 new commits to master: https://github.com/milkymist/migen/compare/0b7dd7bdce96...9d3e21886302
<GitHub72> migen/master f3efd74 Sebastien Bourdeauducq: uio: support memories
<GitHub72> migen/master ab31b4d Sebastien Bourdeauducq: bus: memory initiator
<GitHub72> migen/master 7c6ebcf Sebastien Bourdeauducq: examples/pytholite/uio: demonstrate memories
<GitHub186> [migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/9d3e21886302...784a39943125
<GitHub186> migen/master 784a399 Sebastien Bourdeauducq: examples/memory: use new get_port API
<GitHub186> migen/master 0f6215a Sebastien Bourdeauducq: fhdl/structure: add Memory.get_port API
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<antgreen> just curious: does JTAG specify a throughput (baud?) rate for communication? I've never used a JTAG debugger.
<wpwrak> not sure if there are any "standard" rates. you may just have to go by the data sheets, pick the speed supported by the slowest device in the JTAG chain. if the data sheet doesn't specify a clock, use trial and error.
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<GitHub50> [migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/784a39943125...95122bb7782d
<GitHub50> migen/master 95122bb Sebastien Bourdeauducq: pytholite/io: support memory
<GitHub50> migen/master f42683b Sebastien Bourdeauducq: fhdl/structure/Memory: fix we width
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<GitHub138> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/74721b206f4ce4f145916c3e2c47beb7cc121903
<GitHub138> migen/master 74721b2 Sebastien Bourdeauducq: pytholite: fix import of _Slice
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<GitHub32> [migen] sbourdeauducq pushed 3 new commits to master: https://github.com/milkymist/migen/compare/74721b206f4c...dac0d11e5268
<GitHub32> migen/master d2c61e6 Sebastien Bourdeauducq: sim/generic/multiread: do not return spurious items
<GitHub32> migen/master 27d87c9 Sebastien Bourdeauducq: fhdl/structure: disable we_granularity when larger than width
<GitHub32> migen/master dac0d11 Sebastien Bourdeauducq: actorlib/sim: Dumper
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