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<wolfspraul>
azonenberg: if you were to tape-out your own chip, what packaging would you choose initially?
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<azonenberg>
wolfspraul: if i was making an ASIC? Depends on what it did
<azonenberg>
For low pin counts i'd likely package one or two in DIP-40 and the rest in TQFP-44
<azonenberg>
if it was higher speed or more I/O intensive i'd use 256FTBGA 1mm
<wolfspraul>
256ftbga 1mm is like ftg256?
<wolfspraul>
do you know others who have taped-out and received chips? what packages are commonly chosen or available?
<wolfspraul>
of course I understand it depends on the chip, pin count, speed/protocols etc. etc.
<wolfspraul>
but still, I am trying to find some starting points (such as the ones you just posted - THANKS!)
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<xiangfu>
azonenberg, Hi. I would add a smallest/easiest SPI flash to my mini board. do you have any advice? thanks
<xiangfu>
azonenberg, I have another question on your s60-devboard. you soldering all those components in toaster oven?
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<GitHub15>
[llvm-lm32] jpbonn pushed 1000 new commits to master: http://git.io/eITISw
<GitHub15>
llvm-lm32/master 8f138d1 Chad Rosier: [ms-inline asm] Add a few new APIs to the AsmParser class in support of MS-Style...
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llvm-lm32/master ce353b3 Chad Rosier: [ms-inline asm] Update the end loc for ParseIntelMemOperand....
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llvm-lm32/master 655fa12 Chad Rosier: [ms-inline asm] Use incoming argument rather than hard coding to false....
<azonenberg>
wolfspraul: yes, i would
<azonenberg>
From what i hear DIP40 is most common for low-speed MOSIS chips used for educational stuff
<azonenberg>
but I am more interested in high speed stuff, if i were to get an ASIC fabbed it'd be something with a DDR3 controller and a GHz-range CPU
<azonenberg>
xiangfu: Is this for an xc6slx9 boot flash?
<azonenberg>
W25Q80BV in 8SOIC
<azonenberg>
quad SPI
<xiangfu>
azonenberg, yes. for xc6slx9 boot flash.
<azonenberg>
and yes, i solder everything in the toaster oven
<xiangfu>
thanks I will look into that.
<azonenberg>
You've seen my minimal-s6-tq144 board, right?
<azonenberg>
thats what i used on there
<azonenberg>
the same chip has enouhg capacity for up to the xc6slx25 iirc
<azonenberg>
you can go smaller for a lower end chip if you want but i like to keep only a few values in stock since it makes inventory management simpler
<wolfspraul>
ok and for the high-speed stuff you would choose which package?
<xiangfu>
azonenberg, (toaster oven) it's double side. so solder top side first then the bottom side. so you use the top 2 heat pipe?
<wolfspraul>
didn't get the connection
<wolfspraul>
what's the diff between the ftbga256 you mention and ftg256 ?
<azonenberg>
FTG256 is the Xilinx code for 256ftbga with SAC305 solder balls
<azonenberg>
256ftbga is a generic name for 1mm 16x16 full array BGA
<wolfspraul>
ok
<wolfspraul>
got it
<azonenberg>
FT256 is the xilinx code for the same package with 63/37 solder
<wolfspraul>
thanks!
<azonenberg>
xiangfu: I actually do bottom first
<wolfspraul>
ftg256 is with leaded solder?
<azonenberg>
G = "green" = lead free
<wolfspraul>
wasn't aware of that, I thought it's all lead-free nowadays...
<azonenberg>
A tiny fraction for military etc are not
<azonenberg>
due to reliability concerns
<xiangfu>
azonenberg, (you can go smaller for a lower end chip) what is the lower/smaller chip? I would look into that one too. :-)
<azonenberg>
xiangfu: since that tends to be lightweight components
<azonenberg>
which wont fall off
<azonenberg>
I want to avoid gluing and have surface tension hold stuff on
<azonenberg>
So i do bottom first (facing up) since solder paste isnt sticky until it melts
<azonenberg>
then let cool, flip over, do top side with all the big stuff
<azonenberg>
and rely on surface tension to hold the bottom stuff on
<azonenberg>
and read the configuration guide, it gives bitstream sizes for each fpga
<azonenberg>
w25q40 or 20 will likely be fine for the lx9
<xiangfu>
(and rely on surface tension to hold the bottom stuff on) cool.
<azonenberg>
SPI flash is pretty industry standard
<azonenberg>
the only real variables are package, array size, operating voltage
<azonenberg>
and whether it's true SPI only or supports dual/quad mode
<azonenberg>
the winbond chips normally support quad mode, check the datasheet
<azonenberg>
most micron parts in the M25PE80 family do not
<azonenberg>
i used to use the m25pe80 with spartan3a but 6 supports quad mode that boots 4x faster at the same clock rate
<azonenberg>
xiangfu: and yes, you just have to design the board with that asseembly process in mind
<azonenberg>
Meaning you want lots of surface area for solder and not much mass
<azonenberg>
so avoid, say, big electrolytic caps on the underside
<azonenberg>
and a QFN with thermal pad would be preferred over a TQFP
<GitHub61>
[clang-lm32] jpbonn pushed 1000 new commits to master: http://git.io/ERBEzA
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clang-lm32/master de3832b Sean Silva: tblgen: Migrate clang-tblgen to new TableGenMain API....
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clang-lm32/master 3da76bf Argyrios Kyrtzidis: [libclang] When indexing, invoke the importedASTFile for PCH files as well....
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clang-lm32/master 2ceac2d Bill Wendling: Remove the directory that these are already in....
<xiangfu>
azonenberg, thanks for advice.
<azonenberg>
xiangfu: also that means that if a large heavy connector must be on the underside
<azonenberg>
it needs to be hand soldered after reflow or it'd fall off
<wolfspraul>
but which spi flash do you recommend now? not the micron ones?
<azonenberg>
in a real production process you'd put a dab of high-temperature glue under each part on the underside and have much fewer restrictions
<wpwrak>
azonenberg: i kinda wonder why people still even consider DIP. well, except for cases of extreme mechanical stress perhaps.
<xiangfu>
azonenberg, I am making a very simple board. with only jtag pins out now. :)
<wpwrak>
xiangfu: for making vias on a DIY PCB, try this trick: use a wire with an exactly matched drill, so that the wire will have some friction when you put it through the hole. that make vias relatively painless.
<azonenberg>
wpwrak: the problem is that it sticks up
<azonenberg>
so you cant put it under QFPs
<xiangfu>
there are pre-make tqfp144 pcb . 1.5USD.
<wpwrak>
azonenberg: yup. there are limitations :)
<azonenberg>
wpwrak: and since i use low-profile smt so much i dndt even bother develponig that process
<azonenberg>
since the limitations were such that i'd gain next to nothing
<xiangfu>
I have tired etching qfp144 board. 600DPI printer will short a lot pins. since there are 0.5mm .
<azonenberg>
yes, 0.5mm is at the edge of what i can homebrew too
<xiangfu>
I have a questino on footprint. if the bga ball size is 0.6mm. what is the bga footprint (the ball pad) size? it should be smaller then 0.6mm right?
<wpwrak>
(matches drill/wire) for example, 28 AWG (e.g., OK Industries R28BLK-0100) with a 0.0135" (#80) drill (e.g., Injectorall PC 300C-80)
<wpwrak>
all conveniently available from digi-key ;-)
<azonenberg>
xiangfu: Read the datasheet for recommended sizes
<xiangfu>
azonenberg, the 1200DPI printer will give good result on photo paper.
<azonenberg>
I normally use 0.45mm pads for 0.5mm balls on 1mm centers
<wpwrak>
the drill i mentioned has a 1/8" shaft, which i need for my CNC machine. if you just use a dremel or such, then you can use a straight drill bit, which is cheaper
<xiangfu>
wpwrak, ( making vias on a DIY PCB) yes.
<xiangfu>
wpwrak, (dremel) I have a cheap one. I try to put a driller on it. it shake a lot. not focus on point.
<wpwrak>
(cheaper drills) e.g., injectorall PC300-80. the drill and wire are both thick enough that you won't have to go through a lot of broken drills but still small enough that you get a reasonable via density
<azonenberg>
wpwrak: i usually use carbide bits from drillbitcity.com with straight shanks
<azonenberg>
those are much easier to handle than tiny ones
<azonenberg>
1/8" shanks i meant
<wpwrak>
xiangfu: keep that cheap drill for when you're much older. when you're 90 or so, your hands will probably shake on their own, and then you can blame it on the drill :-)
<wpwrak>
azonenberg: yeah, they also center better in a dremel. at least on digi-key, the price difference is large, though.
<azonenberg>
wpwrak: i buy boxes of 50 for $45
<azonenberg>
they're re-sharpened, not new
<wpwrak>
that sounds scary
<xiangfu>
azonenberg, I am download the datasheet of w25Q40bw. so you would advice winbond-w25Q40bw for my mini slx9 board. I want the easiest chip. :-)
<azonenberg>
bv vs bw is i think just a die revision change so they should be interchangeable
<azonenberg>
and the 40 should be fine for the lx9, check the config guide
<wpwrak>
the prices are amazing, though
<xiangfu>
what about 'W25X SpiFlash Family'? compare to 'Q' which is more common and easy. :)
<azonenberg>
W25Q is the family i've used
<azonenberg>
W25X may not be protocol compatible
<xiangfu>
azonenberg, ok. got it.
<azonenberg>
XC5SLX9 needs 2,742,528 config bits
<azonenberg>
XC6SLX9*
<azonenberg>
So the 2mbit is not enough, the 4 or 8 are fine
<azonenberg>
the LX16 bitstream is 3,731,264 bits so even that should fit in a 4
<azonenberg>
if you want to use the 25 you need 8mbits, 45 needs 16, 75 and 100 need 32, 150 needs 64
<azonenberg>
that's from table 5-5 in UG380
<wpwrak>
but of course, US shipping only :-(
<xiangfu>
oh. I forget the config bits size.
<xiangfu>
ok. I will use W25Q for slx9
<azonenberg>
And of course if you want to store data as well as bitstream
<azonenberg>
you will need more capacity
<azonenberg>
for the lx if you use 4Mbits you'll have the last ~1mbit free
<azonenberg>
the lx9*
<xiangfu>
yes.
<xiangfu>
I think I maybe try make the ftg256 pad a little bit smaller. (for the home-made pcb and 600DPI printer).
<azonenberg>
Yeah, thats not something i would try lol
<azonenberg>
given the prices i pay for batch PCB fab, if i'm dropping $30 on an FPGA i can afford to spend $25 on three dual-layer professionally fabbed PCBs
<azonenberg>
$30 being the going rate for the xc6slx25 around here
<xiangfu>
azonenberg, before do oven-soldering have you do any 'moisture protection' on PCB and CHIP.
<xiangfu>
?
<azonenberg>
I do nothing for pcbs
<azonenberg>
i keep bgas in moisture bags
<azonenberg>
if theyve been out ofr a whlie i bake
<xiangfu>
azonenberg, 'bv vs bw' have different voltage. bv: 3V, bw: 1.8v
<xiangfu>
"25XxxV = 2.7V to 3.6V, 25XxxL= 2.3V to 3.6V, 25QxxBW= 1.65V to1.95V."
<xiangfu>
I will use W25Q40BV :-)
<azonenberg>
oh, i see
<azonenberg>
so B is the die rev
<azonenberg>
and V/W are voltage range
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<kristianpaul>
azonenberg: mips 1 is free of patent?
<kristianpaul>
hi btw
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<mwalle>
Fallenou: wpwrak: i guess we want to know the exact miss address (all 32 bits) in case of a dtlb miss
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<wpwrak>
yes, definitely
<wpwrak>
oops.
<wpwrak>
let me rephrase that ...
<wpwrak>
or rather, confirm it :) (had to think through a few scenarios) i don't think it has to be efficient, though. e.g., for a segfault, you want an exact report, but it's okay if the fault handler has to poke around a bit.
<mwalle>
you mean if the h/w doesn't proivde the exact address, but software can do so by reading some instructions and doing some trickery it is sufficient
<mwalle>
i was just thinking about the preloading TLBVADDR stuff
<mwalle>
which is also the BADADDR register when reading
<mwalle>
so whats missing sth similar to the CAUSE register in MIPS
<mwalle>
(assuming we have two different exception vectors, we could say the exception vector code must take care of saving the cause)
<mwalle>
or calling different functions, etc
<mwalle>
Fallenou: btw its really hard to actually run a given test sequence of instructions deterministically, every now and then the instruction cache needs to be refilled, so a nop or a instruction more or less can change the whole simulation
<mwalle>
atm i hacked the icache to cache 1024 byte lines..
<wpwrak>
(instruction decoding) yes, although that may have a lot of corner cases. but having to retrieve the complete address from some special register would be fine. that would only need to be accessed if we have an actual page table miss, not just a tlb miss.
<mwalle>
wpwrak: whats the difference between PT and TLB miss?
<wpwrak>
so the gateware would provide the raw data and enough for quick page table lookups. then the tlb miss handler walks the page table and - if successful - updates the tlb. if there's a page table miss, then the slow path code would do whatever needs to be done to obtain complete information and then let the kernel worry about the rest
<wpwrak>
see above :)
<mwalle>
ic
<wpwrak>
similar for permission fault. there we also have a "fast path" for cow pages, but that's a lot less critical than tlb misses.
<wpwrak>
so a few extra cycles there won't matter and we can always treat it like a "slow path"