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<
Fallenou>
21:49 < mwalle> Fallenou: if a dtlb miss happens, whats in EA? < it's the address of the instruction causing the miss
<
Fallenou>
well, not exactly, let me explain
<
Fallenou>
exception happen when instruction is in M stage
<
Fallenou>
so at first PC_X gets saved into EA
<
Fallenou>
but one of the first instruction of the exception vector is to substract 4 from EA
<
Fallenou>
so EA ends up with "PC_M"
<
Fallenou>
which is the address of the instruction really causing the miss
<
Fallenou>
there it is
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<
larsc>
so it is pc+4
<
Fallenou>
I find it clearer to say "the address of instruction causing the miss"
<
Fallenou>
well, it depends if you are before or after the substraction
<
larsc>
obviously ;)
<
larsc>
I think what mwalle meant is what's put into EA by the processor when a tlb miss happens
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<
Fallenou>
oh ok, then yes it's not the instruction causing the miss, it's the next one, the one in X during the miss
<
Fallenou>
sorry for the confusion :)
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<
Fallenou>
who is working at ANSSI here ?
* Fallenou
does not remember
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<
larsc>
is that the french NSA?
<
lekernel>
somehow... and they're recruiting like crazy atm
<
Fallenou>
they want to hire something like 200 more persons in the next year ?
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<
mwalle>
ah finally, i get the PAE to create a change request to support $clog2 in localparam, too
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<
Fallenou>
PAE == ?
<
Fallenou>
personnal account engineer ?
<
mwalle>
application engineer
<
mwalle>
product ..
* larsc
just had dinner with some xilinx guys
<
Fallenou>
oh, nice :)
<
Fallenou>
is there somewhere a project about USB analyzer using Milkymist SoC or M1 board ?
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<
mwalle>
larsc: sales guys?
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<
wolfspra1l>
larsc: anything interesting you learned from the dinner?
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<
larsc>
mwalle: yes, sales people
<
larsc>
wolfspra1l: food is expensive in sweden, tha's all ;)
<
mwalle>
larsc: what are you doing in sweden?
<
larsc>
I'm going to give a presentation with them tomorrow about jesd204b
<
lekernel>
try norway, it's even 50% more expensive than sweden :)
<
mwalle>
Fallenou: trying to use the signals in the D stage as read_address input for the tlb ram
<
mwalle>
but i guess i wont meet timing
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<
Fallenou>
good luck, I never had big timing problems while working on the mmu
*lucky*
<
Fallenou>
soon I will try to use draw me a pipeline (after a few debugging sessions) to print analyzes of simple pipeline use cases
<
Fallenou>
too much things to do ... too few hours in the day ...
<
Fallenou>
and a paid job that takes 8 hours per day off my free time
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<
Fallenou>
real life is hard :p
<
mwalle>
All constraints were met.
<
mwalle>
Fallenou: yeah me too ;)
<
Fallenou>
23:34 < mwalle> All constraints were met. < \o/
<
Fallenou>
do you disactivate a lot of cores to speed up synthesis/p&r/etc ?
<
Fallenou>
it helps to speed up :)
<
Fallenou>
but it can show you constraint met when it would not be the case with the full soc :/
<
mwalle>
i know, but i would have bet that even my quick and dirty hack even meet timing
<
Fallenou>
I'm calling it a day
*tired*
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