<azonenberg>
this is a design i had to manually floorplan
<wolfspra1l>
and yes, there are big cutouts in the xc6
<wolfspra1l>
in the top and bottom middle, roughly
<azonenberg>
CPU in yellow, rather overcomplicated but functional interconnect in purple, peripherals in blue
<wolfspra1l>
and I can imagine that xilinx 'cleans up' things in the xc7, because overall I can say that the xc6 looks like a very clean design after 20+ years on it
<azonenberg>
i had to manually exclude the upper left from routing
<wolfspra1l>
so they must have a habit of cleaning up permanently...
<azonenberg>
7 series also eliminates SLICEXs
<wolfspra1l>
(while the latest and greatest features always destroy those efforts, naturally)
<azonenberg>
if you look closely at most of my designs you will see every other column of CLBs is more heavily loaded
<azonenberg>
because my kinds of project tend to use the muxes and adder chains a lot
<azonenberg>
so 7 series will give me much better packing
<wolfspra1l>
that will be a frustrating 1-2 months
<azonenberg>
my xc7 dev board if you're interested
<wolfspra1l>
but then the longer I wait the worse it gets
<azonenberg>
preliminary design is finished, starting schematic capture in a couple of days
<wolfspra1l>
on the other hand, the more xc6 I implement the better my xc7 rewrite will be
<wolfspra1l>
and, finally, every burnt xc7 costs me 140 USD vs. 7 USD for every xc6slx9
<azonenberg>
Lol yes
<azonenberg>
You might want to get it nice and stable on xc6 first
<wolfspra1l>
so for the time being I keep hacking on xc6slx9, until I kick myself
<wolfspra1l>
nah, probably not
<wolfspra1l>
that will take too long
<wolfspra1l>
it's better to speed up, cover as much functionality as possible, to understand the design
<wolfspra1l>
then use the opportunity of the xc7 rewrite to do a lot of things better
<azonenberg>
also looking at the xc6slx4 again
<azonenberg>
wow, that is not a lot of CLBs
<azonenberg>
only five across the whole device
<azonenberg>
and 60 high
<wolfspra1l>
wow that's a big document - SNEAKER
<azonenberg>
One lot of board fab plus components for a prototype will cost me about $1500
<azonenberg>
hopefully i can get some of that back by selling blank boards to other people
<azonenberg>
But i want to be 100% certain i do not need a respin
<azonenberg>
So i'm trying to leave nothing to chance
<azonenberg>
i'm sure there will be mistakes but i hope they won't be fatal
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<wolfspra1l>
what's missing in the SNEAKER doc is a high-level intro paragraph about the purpose/goal of the design
<azonenberg>
Yeah, it wasnt really written for a general audience
<azonenberg>
it was more for me and the few other people involved with it to discuss requirements
<wolfspra1l>
no matter how small the audience, even 1, I think a few-lines intro is good even for yourself to be able to double-check whether the original goals were met or not
<azonenberg>
Yeah, i guess
<azonenberg>
I mean the intention is to be a fairly generic SoC prototyping platform, as well as being something that i can expand my research into since i'm running out of space in the XC6SLX25
<azonenberg>
So I want more of what I already have, basically
<azonenberg>
plus a few extras like USB and HDMI that i couldn't fit in my last board
<wolfspra1l>
I saw the NOR flash there
<azonenberg>
Yeah, I want fast boots and it's a large bitstream
<azonenberg>
so i'm going for BPI rather than SPI
<wolfspra1l>
I think it's fair to say that in milkymist (and before), we learned the hard way that this is not a good long-term solution
<azonenberg>
Can you explain why?
<azonenberg>
You prefer quad SPI?
<azonenberg>
or regular SPI?
<azonenberg>
or what
<wolfspra1l>
too many subtle chip varieties
<azonenberg>
I've specced out a specific component that is on the officially supported list
<azonenberg>
Is your concern that the solution is unstable in general, or that the vendor might stop making that part?
<wolfspra1l>
with what I've learned, I would only do it if I hard a hard timing requirement that would just rule out the fastest spi
<wolfspra1l>
a mix of those
<wolfspra1l>
few people use nor
<azonenberg>
Hmm
<wolfspra1l>
lots of hidden bugs will say hello to you over time
<azonenberg>
You mean parallel NOR
<azonenberg>
because SPI flash is NOR too
<wolfspra1l>
I didn't check carefully what you had there
<wolfspra1l>
so maybe what I say is premature
<azonenberg>
I called for 16-bit wide parallel flash from spansion in a 64-BGA
<wolfspra1l>
your board does not have 'hard' requirements, so in the end it doens't matter much :-)
<azonenberg>
Well, I am hoping for fast boots and quad SPI vs 16-bit parallel is 4x slower
<wolfspra1l>
hard requirements would be a fixed time-to-market, fixed specs (boot time), a certain price point and volume and servicability of the product and users, etc. etc.
<azonenberg>
Doing the math, XC7A200T is 78 Mbits of configuration data
<wolfspra1l>
since all that doesn't exist, use whatever to boot :-)
<wolfspra1l>
yes
<wolfspra1l>
keep calculating
<azonenberg>
let's say max clock rate of 26 MHz
<azonenberg>
4-bit SPI
<wolfspra1l>
that's 78mbit uncompressed?
<azonenberg>
104 Mbps
<azonenberg>
Yes
<wolfspra1l>
how full do you expect your biggest designs to be?
<azonenberg>
So that would translate to just under a second of boot time
<wolfspra1l>
right
<azonenberg>
That's for the 200T, initially i'll use the 100 so half that
<wolfspra1l>
right
<azonenberg>
I'm filling half of the XC6SLX25 with one of my design's several major subsystems
<azonenberg>
I'll probably be using a good chunk of the 100T
<azonenberg>
2/3 or so
<wolfspra1l>
if you are in a car or even worse something faster like plane or rocket, and you need to reboot, 10 ms can bring you a long distance forward already (in the air)
<wolfspra1l>
but I doubt you have that type of requirement
<azonenberg>
No, but one of the intended applications is in network infrastructure so tens of seconds of downtime on power outage would be an issue
<azonenberg>
one second i can handle
<wolfspra1l>
so whether the booting is 0.5s or 2s, does it matter? (the configuration actually, most likely the whole thing you are building will need longer to be fully functional anyway)
<wolfspra1l>
well there you go
<azonenberg>
well, configuration in 500ms is probably doable
<wolfspra1l>
if you have a hard requirement to meet, then that's what you have to do
<wolfspra1l>
and that's where parallel nor has its (expensive) niche
<azonenberg>
if i use the 100T
<azonenberg>
Well that will certainly free up a lot of I/O pins
<azonenberg>
i might do that
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<wolfspra1l>
unless you want to learn about parallel nor, I think it's better to learn about the new high-speed serial options xilinx has in the 7-series
<kristianpaul>
wolfspra1l: how is the burnt count so far?
<wolfspra1l>
the quad stuff is new, I think?
<wolfspra1l>
sorry I am speaking just from memory and not double-checking the docs now...
<wolfspra1l>
kristianpaul: no idea, xiangfu is burning I stay on the software side
<wolfspra1l>
the fpgatools bitstreams themselves have not yet destroyed a single chip, but that's more a sign of how immature it still is
<wolfspra1l>
too bad
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<antgreen>
hey guys - are there any way to simulate mixed verilog/vhdl code with open source tools?
<kristianpaul>
not that i remenber to be honest
<antgreen>
hmm too bad.
<antgreen>
I am wrapping a VHDL moxie implementations with a verilog wishbone wrapper, so I guess I'm stuck with vendor tools.
<azonenberg>
wolfspra1l: i have used quad SPI for spartan6
<azonenberg>
at up to ~20 MHz so 80 Mbps
<azonenberg>
you can go a lot faster in 7 series (66 Mhz for artix7)
<wolfspra1l>
I thought there was something new in 7
<wolfspra1l>
ah ok
<azonenberg>
and up to like 100 in kintex/virtex
<azonenberg>
So that means an uncompressed artix7 could boot in 155ms lol
<azonenberg>
for the 100T
<azonenberg>
and that's at 50 MHz, not even the max
<azonenberg>
i'm switching :P
<wolfspra1l>
155ms with what?
<wolfspra1l>
quad spi?
<azonenberg>
yes
<wolfspra1l>
yes
<azonenberg>
50 MHz (max is 66) * 4 bits is 200 Mbps
<wolfspra1l>
so parallel nor becomes an even smaller niche
<azonenberg>
to load ~31 Mbits
<azonenberg>
Yes
<wolfspra1l>
for the very big devices and hard boot requirements in special gear, you just have to have it
<azonenberg>
so under 150ms if you use the max clock rate
<wolfspra1l>
say a big kintex
<azonenberg>
with no compression
<wolfspra1l>
some have tens of megabytes of config data
<azonenberg>
and yes, for very big devices you dont have much of a choice if you don't want to wait all week
<wolfspra1l>
yes
<azonenberg>
Actuallly
<azonenberg>
It isn't as bad as you might think
<azonenberg>
the largest virtex-7 is still only 448 Mbits of data
<wolfspra1l>
if you fly a rocket at mach-6 or more? :-)
<azonenberg>
So that's just over two seconds on 4-bit parallel
<azonenberg>
or 500ms with 16-bit
<azonenberg>
And lol, if you are doing something like that
<azonenberg>
you configure the fpga before launch
<wolfspra1l>
I think parallel nor has its niche, because it's several times faster - can be
<azonenberg>
or do high-speed partial reconfig
<azonenberg>
Yes, it is
<wolfspra1l>
there's always a need for that somewhere
<wolfspra1l>
but not in our stuff, typically
<azonenberg>
But i was hoping for 500ms from power on to operational
<azonenberg>
and it looks like thats doable wit hquad SPI
<azonenberg>
Thanks for the suggestion :)
<wolfspra1l>
maybe you will struggle more with the rest of the ms anyway
<azonenberg>
looks like i can fit another GPIO port
<azonenberg>
and still have some pins free
<wpwrak>
(m1 and nor) there, a large part of the bad experience comes from picking what's pretty much the worse-case type of NOR configuration on the market. all the other configurations are more robust. the other part was of course a flawed reset design. having said that, unless there is hard evidence that a given task needs parallel NOR, i'd go for SPI.
<azonenberg>
Good to know
<azonenberg>
and i didnt realize the 7 series could use so much higher of a clock rate
<azonenberg>
to config i mean
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<wpwrak>
(worst-case configuration) specifically about the ability to reliably write-protect critical parts of the NOR. the one we have needs a ridiculously small number of cycles to write or even to remove write protection. with SPI, the much larger number of cycles before anything happens protects you against weird events while power is ramping up/dow and your reset is all wrong. of course, as long as you avoid the latter, there's no worry :)
<wpwrak>
so it's really a combination of a bug (the reset) and an unfortunate sourcing decision (the fragile NOR)
<wpwrak>
wolfspra1l: 6 vs. 7: i think that largely depends on what the goals of your project are. if you're trying to postpone any point where results may be judged by people, then 7 (and then 8, etc.) sounds like a good path ;-)
<wolfspra1l>
yes and that is probably why I stay with 6
<wolfspra1l>
because I do want to keep it strictly in a "what really works today?" level
<wolfspra1l>
a chip I can get easily for 7 usd is attractive...
<wolfspra1l>
better than the latest and greatest thing that is somewhere on digikey in sample quantity for 140 USD...
<wpwrak>
yeah, 7 seems to have that elite barrier, too
<wolfspra1l>
which will come down next year
<kristianpaul>
not couting DIY !
<wolfspra1l>
but one by one
<wolfspra1l>
I think xilinx has decided to not compete economically with the market niche of the smaller xc6 devices
<wolfspra1l>
(I mean with the 7 series)
<wpwrak>
you'd be at the level of researchers happily announcing some breakthrough that should be useful to the general public in virtually no time. of course, ten years later, none of that has seen the light of day yet ...
<wolfspra1l>
that means the price of the smallest xc7 will only go down slowly as forced by competition at that level (i.e. only by altera)
<wolfspra1l>
and which in turn means especially the smaller xc6 devices will have a very long lifetime, that is my guess
<wolfspra1l>
whereas the typical slx75 and bigger customer will quickly switch to xc7
<wpwrak>
maybe they also have a long debugging / yield improvement phase and don't actually want a lot of customers at the moment
<wolfspra1l>
sure
<wolfspra1l>
I think industry-wide, 28nm is supply constrained right now :-)
<wolfspra1l>
all the way to Apple etc.
<wolfspra1l>
and I read somewhere that Apple is trying to bully some customers out of tsmc's latest-gen processes with huge orders & investments etc :-)
<wpwrak>
time for samsung to start winning some of those lawsuits :)
<wolfspra1l>
so tsmc will build some fabs/lines/whatever just for apple
<wolfspra1l>
but xilinx is one of tsmc's true lead customers on 28nm. anyway, all moving I think, from reading the news
<wolfspra1l>
I'm just looking at the result, and that is that the slx9 is available with no fuss for 7 USD now
<wolfspra1l>
it came down from 9 USD to 7 USD in the last 4 months alone
<wpwrak>
looks like an excellent choice for getting started with such things
<wolfspra1l>
yes agreed
<wolfspra1l>
that's also a nice and advanced 45nm process (samsung I think)
<wpwrak>
not bad. 9 USD would still be okay for that kind of task. makes a whole PCBA (with simple things only) maybe USD 20, retail perhaps USD 50. something you could make and sell as an fpgatools reference platform.
<roh>
wpwrak: i wonder how much samsung earns per sold iphone
<roh>
simply from providing the soc and memory etc
<wolfspra1l>
and displays
<roh>
that too? hihi
<wolfspra1l>
soc profits must be less now after apples daring multi-billion usd ic investments in recent years
<wolfspra1l>
memory they start investing in too, and displays as well
<wolfspra1l>
good to have 120 billion USD in cash flying around :-)
<wolfspra1l>
and naturally they don't like to feed their own competitor...
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<lekernel>
azonenberg: what software did you use to make those chip floorplans?
<lekernel>
wolfspra1l: have you destroyed fpga's with broken bitstream already?
<lekernel>
sorry, missed the answer in the backlog :)
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<wpwrak>
lekernel: he said that he hasn't yet. he left the destructive work to xiangfu, but using direct thermal execution instead of sneaky software
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<wolfspra1l>
as far as I'm concerned, there is no such thing as a broken bitstream :-)
<wolfspra1l>
maybe some bitstreams and make parts of the chip unconfigurable, yeah :-)
<wolfspra1l>
can make
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<wpwrak>
a bitstream that incorporates certain killer features ....
<GitHub68>
dmp/master 11957b6 Yann Sionneau: Add informations about how to use dmp in README.md
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<lekernel>
azonenberg: tried running linux on your mips softcore yet?
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<azonenberg>
lekernel: no MMU
<azonenberg>
so not an option
<azonenberg>
it runs code compiled with GCC though
<lekernel>
well i'd guess there's nommu linux for mips, no?
<azonenberg>
no idea, i havent looked
<azonenberg>
The main thing is that it isnt on my roadmap and i haven't had the time
<azonenberg>
i'm in the middle of trying to figure out how to add all the peripherals i need for my prototype in the XC6SLX25 so i can give a demo in a month or so
<azonenberg>
without running out of space
<azonenberg>
Because there is no way my artix7 board will be ready before the Jan-Feb time frame
<lekernel>
what do you want to demo?
<azonenberg>
Hopefully? A demonstration of how the isolation capabilities of my proposed architecture will prevent compromise of the kernel or other apps if one app gets pwned
<azonenberg>
Not sure if i can pull that off in a month though
<Fallenou>
ok, if the adaptor does not work, I can still use the VGA cable plugged on my TV which has native VGA input support :)
<wpwrak>
there's also DVI-D, which doesn't use the analog pins. it appears occasionally on the host side, but i'm not sure if it's common on the monitor side.
<Fallenou>
ok let's hope my monitor likes analog stuff :)
<Fallenou>
gn8 here !
<Alarm>
I compile with make-C Flickernoise compile-Flickernoise flickernoise.fbi. I get an error with `rtems_shell_init_env '. See http://pastebin.com/veRjG7cg
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<johndmcmaster>
lekernel: hey
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<lekernel>
hi johndmcmaster
<johndmcmaster>
lekernel: I just wanted to touch base from replying to your e-mail to know if you needed any more info or such from me
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