10:17 <azonenberg> lekernel: So i just finished fully REing the XC2C32A interconnect

10:17 <azonenberg> The flipflop configuration, as well as tri-state I/O buffers, aren't fully figured out yet

10:17 <azonenberg> But I can now fully understand and model arbitrary combinatorial logic that has unidirectional ports only

10:18 <azonenberg> I'm working on writing a fitter/mapper now

10:19 <azonenberg> i think i'm only a few hours of work away from being able to replace any arbitrary combinatorial logic with an XC2C32A using F/OSS tools only (though i'll have to create the netlist in C++ since I don't have HDL support yet)

10:19 <azonenberg> Once i get that working i'll try to figure out how to take iverilog EDIF output and map it to the technology-dependent form i can use on my fitter

10:20 <azonenberg> in parallel, finish figuring out the flipflop config so i can do clocked logic

10:23 <ysionnea1> win 12

13:42 <GitHub76> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/7zCGGw

13:42 <GitHub76> milkymist-ng/master 3d899f0 Florent Kermarrec: cif : fix 2x autorefresh in get_sdram_phy_header

14:17 <wpwrak> azonenberg: i'd agree with ysionnea1 - sounds like a great victory !

14:18 <ysionnea1> ahah

14:27 <wpwrak> it's kinda ironic that the XC2C32A in QFN is 5x5 mm but in a "chip-scale package", it's 6x6 mm

14:58 <azonenberg> wpwrak: lol

14:59 <azonenberg> Just finished I/O bank and macrocell fitting

15:00 <azonenberg> global routing in progress...

15:26 <wpwrak> extending this to all xc2c* should be relatively simple, correct ?

15:27 <wpwrak> then xc2* :)

15:27 <larsc> he said a couple of days ago that some changes are required, but it will be doable with the same codebase

15:27 <larsc> see the log from july 6th

16:07 <kristianpaul> not j1 cpu but interesting target https://github.com/cpldcpu/MCPU

16:55 <GitHub100> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/UzZVvQ

16:55 <GitHub100> migen/master c2d6f14 Sebastien Bourdeauducq: flow/actor/PipelinedActor: clean up

22:33 <azonenberg> kristianpaul: xc2c64a is basically two 32as glued together

22:33 <azonenberg> the only difference is global routing and the dedicated input pin

22:33 <azonenberg> The 128 and larger will need a little more work as the macrocell config is slightly different, not not by a lot