<davidc__>
lekernel: around? Any thoughts on that patch I just sent for group_by_target [I'm about to head to bed; just wanted to see if that was the sane approach]
<davidc__>
w/win 12
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<lekernel>
davidc__, looks good
<lekernel>
i.e. it really should return ({A, B}, [statement1, statement2, statement3]) in that case
<davidc__>
lekernel: yeah; I didn't see a nicer way :). If I think of one, you'll get a patch.
<davidc__>
lekernel: Also, for the SyncFIFO; there's no bypass between ports [there is on the same port]
<davidc__>
(er, on the S6, that is)
<lekernel>
yes, but that should be OK - there is the synchronizer latency after the first write
<lekernel>
which is > 2 cycles of the read clock, so the read port should always get clocked
<davidc__>
lekernel: for the AsyncFIFO; yes - I meant for tweaks to the SyncFIFO so it can be mapped to BRAMs
<lekernel>
ha
<lekernel>
but iirc Xst adds some logic in that case
<lekernel>
that compares the addresses and muxes the read data to a register containing the written data, using the fabric
<davidc__>
lekernel: perhaps. I'll poke at that tonight to see if I can get a large syncfifo into a BRAM. If not; adding the logic manually is easy enough
<lekernel>
yes. but Xst should even do that for you - which is preferable as it could be mapped to hard logic on architectures that might have it
<lekernel>
so I'd say try that first, and look at the manual logic only if there are bugs or other issues
<davidc__>
lekernel: btw - did XST/timing start working again after that patch? [I'd hate to think I broke ISE for you; I know how hard to placate it can be when it gets in one of its moods]
<lekernel>
on the M1 the timing issues have moved to the DVI clocks and are only off by a fraction of a nanosecond - still better than what the expansion board can really do
<lekernel>
there are no problems on the mixxeo
<lekernel>
ha actually it's fine now. not sure what I changed though.
<lekernel>
but several daily ISE breakages is just business as usual anyway ....
<davidc__>
lekernel: heh; I did a 150mhz core clock design in an S3E... everything had to be LOCed by hand [down to the LUT, in some cases] to get it to consistently meet timing
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