<azonenberg>
I created an xc2c32a bitstream that consists of a single NOT gate going from one FTDI GPIO pin to another
<azonenberg>
as well as breaking out both the original and inverted values to two LEDs
<azonenberg>
and successfully verified in hardware
<larsc>
yeay :)
<azonenberg>
The fitting has a lot of room for improvement and has //TODO's everywhere, and right now it only works with in-memory technology-mapped netlists
<azonenberg>
as you can see i'm manually making netlist nodes in C++
<azonenberg>
In technology-mapped form
<azonenberg>
I still have to reverse the bitstream config for the flipflops and global clocking
<azonenberg>
as well as improve my fitter in the event of routing conflicts (right now it just gives up)
<azonenberg>
In parallel with that, i'm going to work on a technology mapper that goes from generic EDIF to this architecture
<azonenberg>
No optimization for now, just make it work
<azonenberg>
Then see if i can hook iverilog up to that and run the same netlist all the way from verilog source to a bitstream
<azonenberg>
Then repeat for clocked logic
<azonenberg>
Then add a static timing analysis engine based on xilinx's published timing numbers (unlike for FPGAs, they actually publish the full speedfile data for the CPLDs in the datasheet... the FPGA timing characteristics in the datasheet do not include full details of routing delays)
<azonenberg>
At that point i'll have a fully functional, but unoptimizing, toolchain
<larsc>
which is still very nice
<azonenberg>
Yeah
<azonenberg>
And room for improvement
<azonenberg>
Right now libcrowbar (the RE and synthesis stuff, CR-II only for now) is 4.4kloc of C++
<azonenberg>
libjtaghal, which includes the JTAG abstraction code, the logic for programming CR-II devices given a bitstream, and a lot of stuff for other device families, is 12.5kloc
<azonenberg>
All BSD licensed and available from that redmine, but not officially released yet
<azonenberg>
i'm holding off on that until i hav esomething more stable
<lekernel>
azonenberg, what about migen-to-edif?
<azonenberg>
lekernel: I want verilog support at some point
<azonenberg>
But any open source tool that can generate EDIF would be a start
<lekernel>
who really wants verilog :)
<azonenberg>
I like it :p
<azonenberg>
Anyway, i'm working bottom up
<azonenberg>
The next step is to create some kind of EDIF file, probably by hand
<lekernel>
you can get edif output from xst
<azonenberg>
and make a mapper that turns it into product term expressions and macrocells etc
<azonenberg>
I could do that too
<azonenberg>
I also have to figure out how to do constraint entry
<azonenberg>
can you put constraints in EDIF?
<azonenberg>
i think not
<lekernel>
not as far as I know
<azonenberg>
so i'd need a UCF or similar file
<azonenberg>
And if i was using iverilog, to support in-source constraints
<lekernel>
migen to edif should really be quite straightforward imo... and you have a bunch of python tools
<azonenberg>
i'd need to modify it to export those constraints to a file along with the EDIF
<azonenberg>
I'd need to learn python first, lol
<lekernel>
plus a lot of "IP cores" that come with migen
<azonenberg>
anyway, i first have to finish a lot of stuff in the fitting and bitstream generation stuff
<azonenberg>
i havent even RE'd the flipflop config fully
<azonenberg>
and there's a lot of corner cases like i mentioned in the fitter
<azonenberg>
and there's no mapper at all
<azonenberg>
But the mapper will take in EDIF
<azonenberg>
That's where i stop
<azonenberg>
any industry standard synthesis tool can make EDIF
<azonenberg>
And any open source one can be coaxed into generating it if you patch enough
<azonenberg>
So i see no need to reinvent the wheel at that point
<azonenberg>
The lower-level stuff is actually important
<azonenberg>
Though I would eventually like a BSD-licensed synthesis tool, iverilog is GPL
<azonenberg>
and you know how i feel about GPL :p
<azonenberg>
i'm all for open source but i want it to be a gift, not taken at gunpoint
<lekernel>
it doesn't work anyway
<azonenberg>
What doesn't work?
<azonenberg>
GPL?
<lekernel>
yeh
<lekernel>
anyway migen is bsd now, so that's another argument for it
<lekernel>
:)
<azonenberg>
Lol, nice
<azonenberg>
But i do want the ability to use existing verilog code eventually
<lekernel>
is there anything open source written in verilog that is worthy of being reused, except lm32 and a couple other things?
<lekernel>
most of it is bitcoin miners lol
<azonenberg>
Some of my stuff, i'd like to think :p
<azonenberg>
And i'm continuing to write new verilog for my research
<azonenberg>
Obviously we can't fit any of that on a CPLD
<azonenberg>
But this will be a good foot in the door for F/OSS EDA
<azonenberg>
then maybe wolfspraul (or someone else) can pick up fpgatools at some point and get that going
<azonenberg>
From what I see, btw, EDIF is a technology dependent format
<azonenberg>
as in, it describes cells rather than boolean logic expressions
<azonenberg>
So i'd need to make a cell library for whatever synthesis tool was being targeted
<azonenberg>
I wonder if i could convince the synthesis tool to output mapped netlists for me :P
<azonenberg>
I doubt it
<azonenberg>
But basically the synthesis tool would output something made of and/nand/nor/or/xor gates and flipflops
<azonenberg>
my mapper would then squish all the combinatorial logic at each level into an and/or array with an optional xor at the end
<azonenberg>
oh also, on the topic of open source HDL
<azonenberg>
Does anyone know of any open source elliptic curve signature schemes implemented for FPGA?
<azonenberg>
I'm specifically looking at signature verification using any elliptic curve scheme, signing will be done elsewhere
<azonenberg>
i just need a way to put a public key into my device and authenticate commands
<azonenberg>
i'm starting to do some fairly complex remote control stuff in my lab and i'd like at least some defense against random people sending packets to it :p
<azonenberg>
and although a HMAC is probably good enough for now, i will definitely need public key crypto eventually
<azonenberg>
(I also need it for my research)
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<GitHub69>
[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/nq_d_g